IBM CPC700, User Manual

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3-8 Processor Interface
3.7 Processor to PLB Master (PCI or Internal Peripherals)
The CPC700 supports single beat (8 bytes or less) and burst (32 byte cache line) read and write accesses
to the PLB. Processor requests that target PLB space are forwarded to the PLB Master interface which ini-
tiates a request on the PLB bus for the associated cycle. The PLB master interface contains a single 32
byte write buffer, a single 8 byte write interface buffer, and a single 32 byte read buffer for processor
accesses to the PLB.
Reads:
Processor to PLB read (single beat and burst) data is buffered in a 32 byte read buffer which captures the
data directly from the PLB bus. All processor to PLB read cycles execute as connected data tenures
between the processor bus and the PLB bus. The processor address tenure remains open until the tar-
geted PLB Slave commits to returning the requested data via the assertion of PLB_AddrAck.
Writes:
All processor to PLB write (burst and single beat) cycles are posted and executed on the PLB at the earli-
est available opportunity. The CPC700’s processor interface contains an 8 byte write interface buffer to
expedite de-allocation of the primary 32 byte write buffer which allows the processor to post a maximum of
two single beat write cycles for transfer to the PLB. All processor to PLB read cycles (single beat and burst)
and write cycles flush the primary 32 byte write buffer and 8 byte write interface buffer (if allocated) con-
tents to the PLB before completing. For more information, see Table 10.
3.7.1 CPC700 Response for Processor to PLB Accesses
The following table corresponds to the state of the processor address bus for a given cycle (which may or
may not be pipelined) and the corresponding response from CPC700.
Once the processor request is accepted, as indicated by the assertion of AACK_N to the processor, data
will be transferred at the earliest available opportunity.
Note: In Table 11., the status of the processor to memory write buffer is a “don’t care.”
.
Table 10. PLB Master Cycles
64-Bit Processor Interface PCI Interface
Single Beat (1-4 Bytes) 1 (Single Beat)
5-8 Bytes 2 Single Beats
32 Byte 1 Eight Word Line
Table 11. CPC700 Response to Processor Transactions to the PLB
Proc
I/F
Proc-PLB
Read
Buffer Proc-PLB
Write
Buffer PLB
Slave
(Snoop)
Response
PLB Rd Deallocated Deallocated Idle Request PLB for read, AACK_N CPU when PLB AdrACK_
and transfer data, or ARTRY_N CPU if PLB Rearbitrate