IBM CPC700, User Manual

Page: 202 / 268

7-8 UART
7.2.1.4 Interrupt Identification Register
The UART prioritizes interrupts into four levels which are recorded in the interrupt identification register.
The levels of interrupt in the order of their priority are receiver line status, received data ready, transmitter
holding register empty, and modem status. When the processor accesses the IIR, the UART records new
interrupts, but does not change its current contents until the access by the processor is complete. The
UART indicates the highest priority interrupt pending to the CPC700 interrupt controller via the IIR.
6 0 Receiver FIFO reset. The 1 that is written into this position is self-clearing.
1 Receiver FIFO reset. A logic 1 written here will clear all bytes in the receiver FIFO and reset all of its
counter logic to 0. The receiver shift register is not cleared by this bit.
7 0 FIFO disabled. Resets both receiver and transmitter FIFOs. Data is automatically cleared from both
FIFOs when changing to and from FIFO and 16450 modes.
1 FIFO enable. Writing a logic 1 here enables both the receiver and transmitter FIFOs.
Table 75. Interrupt Identification Register Description
IIR Bits
Bit # Value Description
0 0
FIFOs disabled (bit 7 of FCR = 0)
1
FIFOs enabled (bit 7 of FCR = 1)
1 0
FIFOs disabled (bit 7 of FCR = 0)
1
FIFOs enabled (bit 7 of FCR = 1)
2 0
Always zero
3 0
Always zero
Table 74. FIFO Control Register Description
FCR Bits
Bit # Value Description