IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-13
5.7 PCI Master Interface (PLB Slave)
This section describes how the PCI interface responds to read and write requests from a PLB master. The
PCI interface decodes and accepts PLB transactions to different address ranges resulting in the genera-
tion of memory, I/O, configuration, interrupt acknowledge and special cycles on the PCI bus.
5.7.1 Commands Generated as a PCI Master
The type of cycle generated on the PCI bus depends on the PLB address, the PLB transfer type, and the
PLB transfer size. The following sections describe the transaction types supported and outlines the transla-
tion of commands from one bus to the other.
The term “single beat” or “1-4 byte” in reference to PLB transfers refers to the M[x]_size=0000b transac-
tion type.
The CPC700 initiates the following commands as a PCI master:
•
I/O Read and I/O Write
This command is generated in response to PLB 1-4 byte read or write requests that decode to one
of the two PCI I/O spaces.
•
Configuration Read and Configuration Write (type 0 and type 1)
This command is generated in response to PLB 1-4 byte read or write requests that decode to the
CONFIG_DATA register.
•
Memory Read
This command is generated in response to PLB 1-4 byte reads that decode to one of the three
PMMs when the PMM is marked as non-prefetchable.
•
Memory Read Multiple
This command is generated in response to PLB 1-4 byte reads that decode to one of the three
PMMs when the PMM is marked as prefetchable. The PCI interface burst reads up to 64 bytes from
the PCI and saves the data in the PCI Master Read Prefetch Buffer. If a subsequent PLB 1-4 byte
read is to an address that hits in the prefetch buffer, then the data is returned to the PLB directly
from the prefetch buffer, and no cycle is generated on the PCI.
•
Memory Write
This command is generated in response to PLB 1-4 byte writes to one of the three PMMs.
•
Interrupt Acknowledge
This command is generated in response to a PLB 1-4 byte read from address FED0_0000h.
•
Special Cycle
Notes:
1. Extra PLB read data may be discarded.
2. If a PCI data phase has discontiguous byte enables, the bridge will convert that phase into two
PLB single-beat writes.
3. If a PCI data phase has contiguous but not all active byte enables, the bridge will convert that
phase into a PLB single-beat write.
Table 43.PCI Interface Responses to PCI Requests (Continued)
PCI Transaction PLB Size PCI, PLB Bus
Action PLB Response PCI Interface
Action