IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-3
5.4 PCI Interface Registers
The PCI Interface registers listed in Table 39., reside at memory mapped addresses in PLB space. See
Section 5.9.1 “PCI Interface Local Configuration Register Descriptions” for additional information.
The PCI Interface configuration registers listed in Table 40., are accessed through an indirect method
employing an address register, PCICFGADR, and a data register, PCICFGDATA. To access one of the PCI
Interface configuration registers, write the appropriate index to register PCICFGADR, then read the data
from or write the data to register PCICFGDATA. See Section 5.9 “Bridge Configuration” for important infor-
mation regarding these registers.
Table 39.PCI Interface Local Configuration Registers
Register Address R/W Description
PMM0LA FF40_0000 R/W PMM 0 Local Address
PMM0MA FF40_0004 R/W PMM 0 Mask/Attribute
PMM0PCILA FF40_0008 R/W PMM 0 PCI Low Address
PMM0PCIHA FF40_000C R/W PMM 0 PCI High Address
PMM1LA FF40_0010 R/W PMM 1 Local Address
PMM1MA FF40_0014 R/W PMM 1 Mask/Attribute
PMM1PCILA FF40_0018 R/W PMM 1 PCI Low Address
PMM1PCIHA FF40_001C R/W PMM 1 PCI High Address
PMM2LA FF40_0020 R/W PMM 2 Local Address
PMM2MA FF40_0024 R/W PMM 2 Mask/Attribute
PMM2PCILA FF40_0028 R/W PMM 2 PCI Low Address
PMM2PCIHA FF40_002C R/W PMM 2 PCI High Address
PTM1MS FF40_0030 R/W PTM 1 Memory Size
PTM1LA FF40_0034 R/W PTM 1 Local Address
PTM2MS FF40_0038 R/W PTM2 Memory Size
PTM2LA FF40_003C R/W PTM2 Local Address
PCICFGADR FEC0_0000 R/W PCI Configuration Address Register
PCICFGDATA FEC0_0004 R/W PCI Configuration Data Register
Table 40.PCI Interface Configuration Register Offsets
PCI Config Register Offset R/W Description
PCIVENDID 01 - 00 R/W Vendor ID
PCIDEVID 03 - 02 R Device ID
PCICMD 05 - 04 R/W Command Register
PCISTATUS 07 -06 R/W Status Register
PCIREVID 08 R Revision ID
PCIINTCLS 09 R/W Interface Class
PCISUBCLS 0A R/W Sub-Class Code
PCIBASECC 0B R/W Base Class Code