IBM CPC700, User Manual

Page: 196 / 268

7-2 UART
7.1 Functional Description
• Runs NS 16550 software
• Registers are identical to the NS16550 register set
• After reset, all registers are identical to the NS16450 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when FIFO mode selected
• Can add/delete standard asynchronous communication bits such as start, stop, and parity to/from the
serial data
• When in character mode, holding and shift registers eliminate the need for precise synchronization
between the processor and serial data
• Full prioritized interrupt system controls
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud rate generator divides the UART serial clock input by 1 to (2
16
-1) and generates
the 16x clock.
Baud rate (bits/s) = (CPC700 SYS_CLOCK / 4) / (16 x Decimal Divisor)
• Receiver uses 5-way oversampling as follows: it samples each serial bit five times, and if at least three
of the samples are 1’s, the bit is determined to be a 1, otherwise it is a 0
• Fully programmable serial-interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no parity bit generation and detection
- 1-,1.5-, or 2-stop bit generation
- Variable baud rate
• Line break generation and detection and false start bit detection
• Internal diagnostic capability:
- Loopback controls for communications link fault isolation
- Break, parity, overrun, framing error simulation