IBM CPC700, User Manual

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3-22 Processor Interface
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[5].
3.15.5 Data Parity Errors
The processor interface may be enabled to detect and report processor data parity errors for processor
write cycle only. Data parity checking is based on odd parity. Odd parity means that an odd number of bits,
including the parity bit, are driven high.
For processor write cycles, the requested transfer will proceed normally with the error condition being
detected and logged if enabled.
If detection is enabled via ERREN1[7], the error will be logged by setting ERRDET1[6], the associated pro-
cessor address and transfer attributes will not be logged, and if enabled via PRIFOPT1[1], MCP_N will be
asserted for a minimum of two clock cycles.
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[6].
3.15.6 PLB Master Error
This section concerns response of CPU interface to a CPU-to-PCI transaction with a target alert.
The processor interface may be enabled to detect and report the assertion of PLB_MErr into the processor
interface’s PLB master. In this document, the processor interface’s PLB master is also referred to as the
60x-PLB master.
PLB_MErr will be asserted into the 60x-PLB master (by the targeted PLB slave) on any 60x-PLB transfer
for which the responding PLB slave encounters an error. In the CPC700, the only PLB slave targets that
could assert PLB_MErr into the 60x-PLB master are the PCI interface and the OPB.
If detection is enabled via ERREN1[2], the error will be logged by setting ERRDET1[2], the associated pro-
cessor address and transfer attributes will not be logged, and if enabled via PRIFOPT1[1], MCP_N will be
asserted for a minimum of two clock cycles.
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[2].
Error address and attributes will be captured in the PLB slave’s error registers (SEAR0 and SESR for the
PCI interface; GESR and GEAR0 for the OPB). If the trapped error status is to be held by the PLB slave for
software observation, ERREN1[3] should be set (once) prior to initiating any processor to PLB accesses.
This bit enables the assertion of the 60x-PLB master’s lockErr output which signals the PLB slave to trap
and hold the error status information in the event an error is encountered.
3.15.7 PLB Slave Error (From PCI Master)
The processor interface detects memory select errors on a write to memory through the PLB slave inter-
face (writes from the PCI bus) and logs the error status and address information in the BESR and BEAR
registers. Memory select errors are not detected on memory reads from the PCI.