IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-1
Chapter 5. PCI Interface
5.1 Overview
The CPC700’s PCI interface provides a mechanism for connecting PCI devices to the local PowerPC pro-
cessor and local memory. This interface is fully compliant with version 2.1 of the PCI Specification.
The PCI Interface communicates with the 6xx/7xx processor and local memory via the Processor Local
Bus (PLB) which is internal to the CPC700. The PCI Interface is both a slave and a master on the PLB.
5.2 Features
• PCI 2.1 compliant
• 32-bit PCI address bus
• PCI bus clock frequency from 25 to 66 MHz
• Supports processor access to all PCI address spaces:
- Single-beat PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes.
- Single-beat PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
• Buffering between PLB and PCI:
- PCI target 32 byte write post buffer
- PCI target 32 byte read prefetch buffer
- PLB slave 32 byte write post buffer
- PLB slave 64 byte read prefetch buffer
• Error tracking/status
• Internal PCI Bus Arbiter for up to 6 external devices at PCI bus speeds up to 33 MHz. Internal arbiter
use is optional and may be disabled for systems which implement an external arbiter supporting a fair
arbitration scheme.
• Support for synchronous and asynchronous clocking between processor and PCI busses. Support for
synchronous clock is limited to 33 MHz PCI bus operation.