IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-29
5.9.3.4 PCI Status Register
Address Offset: 07h - 06h
Width: 16
Reset Value: 0200h
Access: Read/Write (See Table)
The PCI status register is a 16-bit, read/bit-reset register used to record status information for PCI bus
related events (see Table 51.). Bits in this register are only set as a result of specific events occurring on
the PCI bus. They are reset by writing a 1 to the desired bit location. Writing a 0 to a bit location leaves that
bit unchanged.
Table 51.PCI Status Register Bits
Bit(s) Name Description
4:0 Reserved These bits are reserved and return zeros when read.
5 66MHz Capable Indicates that the device is capable of running at 66 MHz. The
CPC700 can be configured to run at 33MHz or 66MHz. This bit is a
0 at reset. The local processor should write this bit to 1 if the
CPC700 is configured for 66MHz PCI operation.
6 UDF Supported Indicates device support of User Definable Features. The CPC700
does not support user selectable configuration items, therefore this
bit is read-only and returns 0 when read.
7 Fast Back-to-Back
Capable Indicates that the PCI target is capable of accepting fast back-to-
back transactions when the transactions are not to the same
agent. The CPC700 target does not accept this type of fast back-
to-back transaction, therefore this bit is read-only and returns 0
when read.
8 Data Parity Error
Detected This bit is set when these two conditions are met:
1. The CPC700 detects a data parity error (PCI_PERR# asserted)
when it is the master on a PCI read cycle, or it is the master when
it samples PCI_PERR# asserted on a PCI write cycle.
2. the Parity Error Response bit (bit 6 of the PCI Command Regis-
ter) is set.
Writing a 1 to this bit resets it to 0.
10:9 DEVSEL Timing PCI_DEVSEL# response timing. The CPC700 asserts
PCI_DEVSEL# on the second clock (also known as medium
response time) after PCI_FRAME# is asserted by a PCI master
attempting to access memory on the PLB side of the bridge. These
bits are read-only and always return 01b when read.
11 Signaled Target-
Abort The CPC700 sets this bit whenever it terminates a PCI cycle for
which it is the target with target abort.
Writing a 1 to this bit resets it to 0.