IBM CPC700, User Manual

Page: 192 / 268

6-8 Clock, Power Management, and Reset
6.5.4 PLL Configuration Access Register (CPRPLLACCESS)
Address: FF50_090Ch
Width: 32 bits
Reset Value: 0000_0000
Access: Read /Write
This register controls access to the PLL Tuning Control register. Setting bit 0 to a “1” allows the PLL Tuning
Control register to be written.
6.5.5 PLL Tuning Control Register (CPRPLLTUNE)
Address: FF50_0910h
Width: 32 bits
Reset Value: Depends on Strapping bit configuration
(104F_484F - for 25-50MHz PCI bus)
(104F_B44F - for 49-67MHz PCI bus)
Access: Read - Returns the current contents of the register
Write - The act of writing this register will cause an immediate reset on RESET_OUT_N.
See Section 6.1.1, “PLL Tuning” for important information regarding this register.
Note: If changes from the default values are required, contact your IBM representative for proper values for
this register.
Table 67. PLL Configuration Access Register
Bit Name Default Description
0 PLLWRENABLE 0 PLL Configuration Register Access Enable
1:31 0 Reserved - Reads return 0
Table 68. PLL Tuning Control Register
Bit Name
Default
25-50MHz PCI Default
49-67MHz PCI
Description
0:2 PLL0_RANGEA 000 000 PLL 0 RangeA
3:5 PLL0_RANGEB 100 100 PLL 0 RangeB
6:9 PLL0_MULT 0001 0001 PLL 0 Multiplication Factor
10:15 PLL0_TUNE 001111 001111 PLL 0 Tuning Bits
16:18 PLL1_RANGEA 010 101 PLL 1 RangeA
19:21 PLL1_RANGEB 010 101 PLL 1 RangeB
22:25 PLL1_MULT 0001 0001 PLL 1 Multiplication Factor
26:31 PLL1_TUNE 001111 001111 PLL 1 Tuning Bits