IBM CPC700, User Manual

Page: 185 / 268

CPC700 User’s Manual—Preliminary 6-1
Chapter 6. Clock, Power Management, and Reset
The CPC700 provides Clocking, Power Management, and Reset (CPR) controls for selected on-chip func-
tions.
6.1 CPC700 Clock Control
The CPC700 clocking is controlled by two PLLs which minimize the clock skew between the internal
latches of the CPC700 and the external devices in the system. The PLL usage is outlined in Table 61.
PLL1 is only used when the PCI interface is used in asynchronous mode. When in synchronous mode,
PLL1 is placed in bypass mode via the pin strapping indicated in Table 63, and the PCI clock input pin are
pulled to ground.
6.1.1 PLL Tuning
The PLL contains a number of bits which may be used for tuning it when jitter is at unacceptable levels. The
default factory recommended tuning bit settings are typically all that is needed, but in noisier environments,
it may be necessary to change the tuning bits during operation; however, once the tuning bits are changed,
the PLL must be reset, which also necessitates that the rest of the system be reset. Once the tuning bits
are changed, the CPR will generate a reset on the RESET_OUT_N pin, which must be used to drive the
processor’s HRESET# logic. The CPC700 internal latches will be reset at the same time as if a System
Reset had occurred, with the exception that the PLL tuning bits will retain the values just written to them.
Driving a soft reset to the processor via the RESET_OUT_N pin would not allow the CPC700 strapping to
be read properly after the tuning bits are changed. See Section 6.3.2, “Internal Peripheral Reset Control”.
The system designer must ensure that the RESET_OUT_N output from the CPC700 does not cause the
SYS_RESET_N input to the CPC700 to be driven low. This would cause the tuning bits to be reset to their
factory defaults.
Access to the tuning bits in the PLL Tuning Control register requires that the PLL Configuration Access
Enable bit be set in the PLL Configuration Access register. Modification of the PLL tuning bits may only be
done once after power on.
In addition to the tuning bits, other PLL control signals are accessible for changing PLL frequency ranges.
See Section 6.5.4, “PLL Configuration Access Register (CPRPLLACCESS)”, and Section 6.5.5, “PLL Tun-
ing Control Register (CPRPLLTUNE)” for additional information.
Table 61. PLL Usage
PLL Input Frequency Output Frequency Usage
PLL 0 SYS_CLOCK (=PCI_CLK) =
1/2 CPU bus clock SYS_CLOCK UART, IIC, and Timers, Sync PCI IFC
SYS_CLOCK x 2 All Other Cores (especially CPU bus IFC)
PLL 1 25MHz to 67MHz (PCI_CLK) Same as input Async PCI Interface