IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-13
4.5.7.1 Self-Refresh operation
The SDRAM Controller supports self-refresh operation for applications desiring lower power. Note that only
the SDRAM memory is affected by self-refresh operation, the SDRAM controller itself does not enter any
specific power saving mode. Self-refresh operation is only available on bank 4.
In order for the SDRAM controller to place the SDRAM in self-refresh mode, the SDRAM controller must
first be enabled (DC_EN set to 1 in the MCOPT1 register), with the appropriate bank’s MEMTYP set to
b’10’ (SDRAM).
Once enabled, the SDRAM controller may be placed in self-refresh mode anytime following the memory
initialization sequence. To guarantee that the initialization sequence has completed, a minimum wait of 400
processor bus clock cycles following the setting of the DC_EN bit must be observed before enabling self-
refresh. After initialization has completed, self-refresh can be enabled by setting the PM_EN and
SLFREFEN bits to 1 in the MCOPT1 register.
Upon entering self-refresh the SDRAM controller will clear the SLFREFEN bit. The SDRAM controller will
maintain the SDRAM in self-refresh (CKE low) until an access (read/write) to the SDRAM is requested by
the system. Resetting the PM_EN bit or SLFREFEN bit will not cause the SDRAM controller to exit self-
refresh. Upon receiving the request, the SDRAM controller will exit self-refresh and wait a minimum of 12
clock cycles (SD_SREX field of SDTR1 register) before performing the access.
Once the SDRAM controller has exited self-refresh mode, it will not re-enter self-refresh until SLFREFEN
is set again.
As indicated above, it is not necessary to clear the SLFREFEN as the SDRAM controller will clear this bit
upon entering self-refresh.
4.5.8 Mode Register Write Command
The Mode Register Write command is issued during the Initialization Sequence to configure the SDRAM
operating mode. Once the SDRAM operating mode has been configured, normal memory accesses are al-
lowed to proceed.
The Mode Set command vector is placed on the external memory address bus during the Mode Register
Write Command window. The Mode Set command vector consists of four fields: Options - MA(11:7), CAS_
Latency - MA(6:4), Wrap Type - MA(3), and Burst Length - MA(2:0). For the SDRAM controller, the Options
field is hardcoded to b’00000’ to enable the Mode Register Set Command, the CAS_ Latency field is con-
figurable via the SD_CASL bits in the SDTR1 register allowing for a CAS_ latency of 2 or 3 to be selected,
the Wrap Type field is hardcoded to a b’0’ to select sequential wrap addressing, and the Burst Length field
is generated based on whether the memory is configured for 32 or 64-bit width (as set via the SD_WDTH
bit in the ECCCF register) and configures the SDRAM for burst of 8 or burst of 4 respectively.
Table 26. Mode Set Command Vector
MA
11 MA
10 MA
9 MA
8 MA
7 MA
6 MA
5 MA
4 MA
3 MA
2 MA
1 MA
0
64-bit bus 0 0 0 0 0 0 1 SD_CASL 0 0 1 0
32-bit bus 0 0 0 0 0 0 1 SD_CASL 0 0 1 1