IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 3-21
3.15.2 Memory Select Error - Processor Access
The processor interface may be enabled to detect and report memory select errors for processor to mem-
ory read and write transfers. A memory select error will be generated for any access which attempts to
address memory which is not valid. This includes addresses out of range, and writes to ROM/Peripheral
space when configured as read only.
On a processor read, if a memory select error is detected, the processor interface will complete the access
and return all 1’s (that is each bit the processor data bus will be set to 1) with the TA_N assertion.
On a processor write, if a memory select error is detected, the processor interface will complete the access
and discard the write data.
If detection is enabled via ERREN1[1], the error will be logged by setting ERRDET1[1], the associated pro-
cessor address will be logged in CPUERAD[0:31], the associated processor transfer attributes will be
logged in CPUERAT[0:7], and if enabled via PRIFOPT1[1], MCP_N will be asserted for a minimum of two
clock cycles.
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[1].
NOTE: ERREN1[1] only enables the detection of memory select errors for processor to memory accesses.
3.15.3 Flash Write Errors
The processor interface may be enabled to detect and report flash write errors for processor to memory
write transfers which target the ROM/Peripheral controller as well as banks for which flash writes are not
enabled. This event will also trigger a memory select error if ERREN1[1] is set.
On a processor write, if a flash write error is detected, the processor interface will complete the access and
discard the write data.
If detection is enabled via ERREN1[5], the error will be logged by setting ERRDET1[4], the associated pro-
cessor address will be logged in CPUERAD[0:31], the associated processor transfer attributes will be
logged in CPUERAT[0:7], and if enabled via PRIFOPT1[1], MCP_N will be asserted for a minimum of two
clock cycles.
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[4].
NOTE: ERREN1[4] only enables the detection of flash write errors for processor to memory accesses.
3.15.4 Address Parity Errors
The processor interface may be enabled to detect and report processor address parity errors. Address par-
ity checking is based on odd parity. Odd parity means that an odd number of bits, including the parity bit,
are driven high.
For processor read, write, and address only cycles, the requested transfer will proceed normally with the
error condition being detected and logged if enabled.
If detection is enabled via ERREN1[6], the error will be logged by setting ERRDET1[5], the associated pro-
cessor address and transfer attributes will not be logged, and if enabled via PRIFOPT1[1], MCP_N will be
asserted for a minimum of two clock cycles.