IBM CPC700, User Manual

Page: 162 / 268

5-30 PCI Interface
5.9.3.5 PCI Revision ID Register
Address Offset: 08h
Width: 8
Reset Value: 01h
Access: Local Write/Read, PCI Read Only
The revision ID register is an 8-bit register used to hold the current incremental revision numberof the PCI
interface. The reset value is the version of the PCI interface as well as the revision level of the CPC700.
Tthe local CPU (PLB master) has read/write access to this register.
.
5.9.3.6 PCI Class Register
Address Offset: 0Bh - 0Ah - 09h
Width: 24
Reset Value: 060000h
Access: Local Read/Write, PCI Read Only
12 Received Target-
Abort The CPC700 sets this bit whenever a PCI cycle for which it is the
master is terminated with target abort.
Writing a 1 to this bit resets it to 0.
13 Received Master-
Abort This bit is set whenever the CPC700 terminates a PCI cycle for
which it is the master with master abort.
Writing a 1 to this bit resets it to 0.
14 Signaled System
Error Signaled system error. The CPC700 sets this bit if it asserts
PCI_SERR# (see the section on Error Handling for causes of
PCI_SERR# assertion)
Writing a 1 to this bit resets it to 0.
15 Detected Parity Error The CPC700 sets this bit whenever it detects a PCI bus parity
error, regardless of the setting of any enable bits (i.e. this bit is non-
maskable). The following events set this bit:
1. PCI address bus parity error detected when the CPC700 is a tar-
get.
2. PCI data bus parity error detected when a PCI master writes to
PLB memory (the CPC700 is the target).
3. PCI data bus parity error detected when the CPC700 masters a
PCI read cycle.
Writing a 1 to this bit resets it to 0.
Table 51.PCI Status Register Bits (Continued)
Bit(s) Name Description