IBM CPC700, User Manual

Page: 218 / 268

8-12 IIC
8.4.10 Interrupt Mask Register
This register should be set before interrupts are enabled in the mode control register.
8.4.11 Transfer Count Register
This register can be read to determine the actual number of bytes sent or received in a master or a slave
operation.
Master transfer count bits(5:7) are defined as follows:
0x0 - zero bytes transferred
0x1 - one byte transferred
0x2 - two bytes transferred
0x3 three bytes transferred
0x4 - four bytes transferred
0x5 through 0x7 - reserved for future use
Bits 4:7 are cleared when the pending transfer bit in the control register is set to a logic 1.
Slave transfer count bits(1:3) are defined as follows:
0x0 - zero bytes transferred
Table 91. IIC Clock Divide Programming
CPC700 SYS_CLOCK Frequency Range (MHz) N (Hex)
= 20 1
20 < ƒ
≤
30 2
30 < ƒ
≤
40 3
40 < ƒ
≤
50 4
50 < ƒ
≤
60 5
Table 92. Interrupt Mask Register
Register ‘FF6X_000D’ - Interrupt Mask
bit 0 Enable IRQ on slave read complete. The interrupt is activated upon receipt of a STOP during a
slave read on the IIC bus. When STOP is received during a read, the slave read complete bit, bit 0
of the extended control and slave status register, is also set to a logic 1.
bit 1 Enable IRQ on slave read needs service. The interrupt is activated upon receipt of a slave read on
the IIC bus and the slave buffer was empty or went empty and more data was requested on the
IIC bus. The slave read needs service bit, bit 1 of the extended control and slave status register, is
also set to a logic 1.
bit 2 Enable IRQ on slave write complete. The interrupt is activated upon receipt of a STOP during a
slave write on the IIC bus. When STOP is received during a write, the slave write complete bit, bit
2 of the extended control and slave status register, is also set to a logic 1.
bit 3 Enable IRQ on slave write needs service. The interrupt is activated when the slave buffer
becomes full during a slave write on the IIC bus. When the buffer becomes full during a write, the
slave write needs service bit, bit 3 of the extended control and slave status register, is also set to
a logic 1.
bit 4 Enable IRQ on halt executed.
bit 5 Enable IRQ on incomplete transfer.
bit 6 Enable IRQ on transfer aborted.
bit 7 Enable IRQ on requested master transfer complete.