IBM CPC700, User Manual

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1-6 CPC700 User’s Manual—Preliminary
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC
processor and local memory. This interface is compliant with version 2.1 of the PCI Specification. Features
of this core include:
• 32-bit PCI address bus
• PCI bus clock frequency from 25 to 66MHz
• Supports processor access to all PCI address spaces:
- Single-beat PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes.
- Single-beat PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
• Buffering between PLB and PCI:
- PCI target 32-byte write post buffer
- PCI target 32-byte read prefetch buffer
- PCI master 32-byte write post buffer
Table 1. Address Map
Function Sub Function
Start
Address End
Address
Size
Local Memory/Peripherals
1
0000 0000 7FFF FFFF 2GB
PCI Core Space
8000 0000 FF4F FFFF 2GB - 11MB
PCI Memory 8000 0000 F7FF FFFF
PCI I/O F800 0000 F800 FFFF
Reserved F801 0000 F87F FFFF
PCI I/O F880 0000 FBFF FFFF
Reserved FC00 0000 FEBF FFFF
PCI Configuration Registers FEC0 0000 FEC0 0004
PCI Interrupt Acknowledge FED0 0000 FEDF FFFF
Reserved FEE0 0000 FF3F FFFF
PCI local Configuration Registers FF40 0000 FF40 003C
Device Configuration
Register (DCR) Space
FF50 0000 FF5F FFFF 1MB
Processor Interface Registers FF50 0000 FF50 0004
Memory Controller Registers FF50 0008 FF50 000C
OPB Macro Registers FF50 0810 FF50 0818
PLB Macro Registers FF50 0850 FF50 085C
Interrupt Controller FF50 0880 FF50 08A0
Clock and Power Management FF50 0900 FF50 0914
Internal Peripherals
FF60 0000 FF7F FFFF 2MB
UART0 FF60 0300 FF60 0307
UART1 FF60 0400 FF60 0407
IIC0 FF62 0000 FF62 0010
IIC1 FF63 0000 FS63 0010
Timers FF65 0000 FF65 00FC
Local Memory/Peripherals
1
FF80 0000 FFDF FFFF 6MB
Boot ROM FFE0 0000 FFFF FFFF 2MB
1. The Local Memory/Peripheral areas of the memory map may be configured for SDRAM, ROM, or Peripherals.