IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 8-3
The slave data buffer is an exact copy of the master data buffer. The data contained in this buffer is either
received from the IIC bus when the IIC interface is addressed as a slave during a write operation, or is sent
out onto the IIC bus when the IIC interface is addressed as a slave during a read operation.
The Lo and Hi master address registers are used to form the address that the IIC interface transmits on the
IIC bus. The Hi master address register is only used for 10-bit addressing and need not be programmed in
7-bit addressing mode.
The control register is used to start and stop IIC interface master transfers on the IIC bus. When a transfer
is started, the IIC interface uses the values in this register to determine the type and size of the transfer.
The mode control register is used to set the major modes of operation on the IIC bus. In addition, the mas-
ter and slave data buffers can be forced into the empty state.
The status register contains a summarized view of the current state of the IIC interface.
The extended status register contains additional information describing the current state of the IIC inter-
face.
The Lo and Hi slave address registers are used to program the slave address of the IIC interface. The Hi
slave address register is only used for 10-bit addressing and need not be programmed in 7-bit addressing
mode.
The clock divide register is used to establish a frame of reference between the IIC interface’s system clock
and the IIC bus’s serial clock.
The interrupt mask register is used to control which interrupts can be issued.
The transfer count register is used to indicate the number of bytes actually transferred across the IIC bus in
a master or a slave operation.
The extended control and slave status register provides additional control of some internal IIC interface
functions and contains the status for slave operations.
The direct control register provides direct control and monitoring of the IIC clock (SCL) and data (SDA) sig-
nals for error recovery functions. These signals are IIC0_SCL and IIC0_SDA for the IIC0 interface, and
IIC1_SCL and IIC1_SDA for the IIC1 interface.
8.4 IIC Register Definitions
The following sections contains the bit definitions for the various registers in the IIC interface.
Note: Register bit definitions are shown in big-endian notation. (bit-0 is msb and bit 7 is lsb.)
8.4.1 Master and Slave Data Buffers
The master data buffer is a FIFO, not a register in the conventional sense. It is four-bytes deep by one-byte
wide and can be accessed via byte or double-byte (halfword) operations. When the buffer is written with
one byte, the byte is put into the FIFO and the hardware automatically pushes the byte into deepest unoc-
cupied location in the FIFO. The byte advances one FIFO stage per clock. Thus, if the FIFO is empty, a
total of four clocks are needed, one for each stage, for the byte to walk to the first stage of the FIFO. This
timing is important to consider when the program is going to try to read the FIFO immediately after data
was written. When a master transfer is requested, the IIC interface handles this latency. When the buffer is
written with two bytes via one double-byte access, and the FIFO is empty, byte 0, the most significant byte