IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-3
4.3 Memory Controller Registers
The memory controller registers are accessed through an indirect method employing a configuration
address register, MEMCFGADR, and a configuration data register, MEMCFGDATA. To access one of the
memory controller registers, write the appropriate index to register MEMCFGADR, then read the data from
or write the data to register MEMCFGDATA. All configuration accesses from the processor must be 4 Byte
aligned, otherwise an error will be generated and the cycle not performed.
Table 22 lists the offsets for the various configuration registers located within the memory controller.
Table 21. Memory Controller Register Addressing
Register Address R/W Description
MEMCFGADR FF50_0008 R/W Memory Controller Configuration Address Register
MEMCFGDATA FF50_000C R/W Memory Controller Configuration Data Register
Table 22. Offsets for Memory Controller Registers
Register Offset R/W Description
MCOPT1 20 R/W Memory Controller Options 1
MBEN 24 R/W Memory Bank Enable
MEMTYPE 28 R/W Installed Memory Type
RWD 2C R/W Bank Active Watchdog Timer
RTR 30 R/W Refresh Timer Register
DAM 34 R/W DRAM Addressing Mode
MB0SA 38 R/W Memory Bank 0 Starting Address
MB1SA 3C R/W Memory Bank 1 Starting Address
MB2SA 40 R/W Memory Bank 2 Starting Address
MB3SA 44 R/W Memory Bank 3 Starting Address
MB4SA 48 R/W Memory Bank 4 Starting Address
MB0EA 58 R/W Memory Bank 0 Ending Address
MB1EA 5C R/W Memory Bank 1 Ending Address
MB2EA 60 R/W Memory Bank 2 Ending Address
MB3EA 64 R/W Memory Bank 3 Ending Address
MB4EA 68 R/W Memory Bank 4 Ending Address
SDTR1 80 R/W SDRAM Timing register 1
RBW 88 R/W ROM Bank Width
FWEN 90 R/W Flash Write Enable
ECCCF 94 R/W ECC Configuration