IBM CPC700, User Manual

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3-12 Processor Interface
Requests from the processor are treated as implied requests for access to system memory. As such, arbi-
tration of processor and PCI requests indicates that the associated device receiving the grant is guaranteed
the next access to system memory once any in-progress access completes. For PCI accesses to system
memory, the PCI/Snooper, once granted the processor address bus, retains ownership of the address bus
for the duration of the PCI to memory transfer. Specifically, this applies to PCI Burst accesses, during which
the processor address bus ownership is required to allow snooping of burst accesses which attempt to cross
a cache line boundary.
3.10 Broadcast Snoop Cycles
The CPC700 supports PCI accesses to system memory via the PLB Slave interface. Memory coherency is
maintained by the internal snoop engine. PCI requests which address system memory are accepted and
snooped in the processor's L1 cache before allowing the access. Snoop cycles to the processor are gener-
ated on behalf of the PCI interface by the internal snooper. The following table lists the corresponding snoop
transfer type for PCI accesses to system memory.
To perform a snoop cycle to the processor, the snoop engine must arbitrate for the processor bus. Once
access has been granted and the address bus is available, the snoop engine will proceed with the snoop
cycle. If a processor access to system memory is in progress, the transfer is allowed to complete. If a pro-
cessor access to the PLB is in progress and a PLB Slave device has not acknowledged the start of the PLB
cycle, the PLB Master interface of the processor interface will abort the PLB cycle and the processor inter-
face will ARTRY_N the processor to gain control of the processor address bus to perform the pending snoop
cycle.
Table 15. Processor Snoop Transfer Types
PLB Bus Cycle Processor Bus Snoop Cycle Processor Snoop TType[0:4]
Memory Read Single-Beat Read 01010
Memory Write Single-Beat Write
with Flush 00010