IBM CPC700, User Manual

Page: 142 / 268

5-10 PCI Interface
5.6.2.3 Read Prefetching
The PCI interface attempts to prefetch data to maximize burst throughput of PCI read requests. Read
prefetching is done only in response to Memory Read Multiple commands (Memory Read Line causes
prefetching to the next 32-byte boundary only). This prefetch buffer is 32 bytes (In the CPC700, the mem-
ory controller also has a 32-byte prefetch buffer, for a total of 64 bytes of prefetch buffering).
If a PCI master is reading from the read buffer, and a PLB read is in progress, data is passed to the PCI
while it is being filled from the PLB. If the read buffer goes empty long enough for the PCI subsequent
latency timer to expire, the PCI is target disconnected. If the read buffer fills up, the PLB cycle is master ter-
minated.
If a PCI master is reading from the read buffer, and a PLB read is not in progress, and the PCI master
posted write buffer is not empty, then the PCI is target disconnected when the read buffer becomes empty.
If a PCI master is reading from the read buffer, and a PLB read is not in progress, and the PCI master
posted write buffer is empty, then when the buffer becomes half empty, a new PLB read is initiated.
A PLB read prefetch may be master aborted if the PCI master does a master disconnect while the PLB
read is pending, but not yet acknowledged.
Prefetched data is discarded if a write is accepted from either the PLB or the PCI. In addition, a PCI master
read that misses the prefetch buffer causes the current read data to be discarded and the new request to
be serviced.
5.6.2.4 Byte Enable Handling
PCI byte enables are treated as don’t cares for PCI reads. The PCI interface performs word burst or single-
beat reads on the PLB regardless of the byte enables presented by the requesting PCI master. Note: this
rule assumes that all PLB memory is prefetchable and that all accesses to PLB memory are non-destruc-
tive.
5.6.2.5 Handling of Writes from PCI Masters
The PCI interface responds to Memory Write and Memory Write and Invalidate commands. All PCI master
writes are posted. A 32 byte write buffer is used for this purpose (in the CPC700, the memory controller
also has a 32-byte write post buffer, thus a total of 64 bytes can be write posted). The write buffer accepts
up to two separate PCI write transactions. Two single-beat writes; one eight-word burst write; or a combina-
tion of a single-beat and a burst write may be posted. If the write buffer is full, new writes are retried until
buffer space becomes available.
Note: The maximum number of two-posted transactions is as viewed from a PCI master’s perspective. The
actual number of writes performed on the PLB may be more than two, depending on the setting of byte
enables of write burst data (see Section 5.6.2.6 “Byte Enable Handling” ).
The PCI interface begins a PLB write request as soon as a PCI master write has completed on the PCI bus
or a bursting PCI master has written at least three words of data. The CPC700 continues to receive data
from a bursting PCI master while it is transferring data to the PLB. If the write post buffer fills up, then the
PCI master is target disconnected. If the write post buffer goes empty, then the PLB cycle is master termi-
nated.
All posted writes must complete on the PLB before a read initiated by either a PCI or PLB master is
allowed to proceed. All posted write are run on the PLB in the same order that they are received from the
PCI.