IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-9
5.6.2 Handling of Reads from PCI Masters
The CPC700 responds to PCI Memory Read, Memory Read Line and Memory Read Multiple commands.
The PCI interface initiates all PLB reads as single-beat or word burst transfers. Memory Read generates a
PLB single-beat read while Memory Read Line and Memory Read Multiple generate PLB word bursts. In
the case of Memory Read Line, the PCI interface encodes a burst length on the M[x]_BE pins of the PLB,
which corresponds to the number of words from the start address to the end of a 32-byte boundary. How-
ever, it will not actively terminate the burst when the encoded number of words has been transferred (typi-
cally the target will). If the starting address is the last word on a 32-byte boundary (typically should not
occur), the PCI interface executes a single-beat read. For Memory Read Multiple, the PCI interface sets
M[x]_BE to all zeros, signifying a variable length burst.
5.6.2.1 Read Buffer
The PCI interface has a read buffer that all read data (including delayed read and prefetched data) is
stored in when it is received from the PLB and before it is passed to the PCI. The size of the read buffer is
32 bytes, and can hold one transaction. In addition, the 60x-PLB interface contains an additional 32-byte
buffer providing a total of 64-byte of read buffer space.
5.6.2.2 Delayed Reads
The PCI interface guarantees the PCI initial target latency requirement by retrying the PCI cycle if the PLB
request is not acknowledged or the first beat of data is not returned from the PLB slave within the initial tar-
get latency requirements for a PCI target.
If the PCI interface must retry the PCI cycle, it continues the read on the PLB side, and puts the data into
the read buffer. This is referred to as a delayed transaction by the PCI specification. Additionally, if a PCI
master requests a read while there are PCI master writes posted, a delayed read is initiated. These posted
writes are completed on the PLB bus before the read is run. The PCI interface continues to accept (post)
PCI master writes (buffer space allowing) while a delayed read is in progress. These writes complete on
the PLB after the read (even though they complete on the PCI before the read - see PCI 2.1 section 3.11,
Special Design Considerations).
When a PCI master re-requests the delayed read, the data is passed directly out of the read buffer. While
the PCI master is accepting the delayed read data, the PCI interface may begin prefetching more read data
if the PCI Master Posted Write buffer is empty. See Read Prefetching below for more details.
If some of the delayed read data is passed to the PCI master, but the PCI cycle is disconnected while the
read buffer still contains more data, then the data is considered prefetch data - it is not considered delayed
read data.
The PCI interface can hold one delayed read transaction. It retries all other PCI master reads until the
delayed read completes on the PCI. The read buffer discards data from a delayed read under only one
condition. The PCI Discard Timer is used to track the amount of time it takes for a PCI master to re-request
the read. If the PCI master does not re-request the read in 2
15
PCI clocks (about one millisecond for a
33MHz PCI clock), the PCI interface discards the delayed read data. This timer begins counting at the
beginning of the initial PCI cycle (Delayed Read Request). Note that if the PCI interface is used in a system
on which the PLB target (memory) max latency (including PLB arbitration) is a significant portion of the
timer’s duration, the timer may expire despite normal bus operation (this is a bad thing). One alternative to
this problem is to disable the PCI Discard Timer.
If a delayed read is rearbitrated or burst terminated on the PLB (rare occurrence), the PCI interface will not
repeat the request until the PCI master re-requests and only then if the PCI master requests more data
than is already buffered.