IBM CPC700, User Manual

Page: 74 / 268

4-2 Memory Controller
• Programmable address mapping
• Peripheral Device pacing with external “Ready”
ECC:
• Single-bit error correct and double-bit error detect on memory reads
• Aligned nibble error detect
• Single bit address error detect
• 8 check bits support 32 or 64-bit data bus widths
• Support for mixing ECC and Non-ECC DIMMs in the same system
• ECC checking may be disabled
4.2 Memory Controller Block Diagram
A block diagram of the CPC700 memory controller is shown in Figure 8.
Figure 8. Memory Controller Block Diagram
Configuration Registers
ECC
Control
ROM
SDRAM
Read
Write
MEM read
MEM write
register
Control
Address
data-path
RAS/CAS,
OE/WE/ALE,
bank enables,
etc.
data path
data path
control signals
data path
data path
DCR Bus
SRAM
Peripherals
outputs
Read Data Path
Write Data Path
Memory Controller Interface
External Memory/Peripheral Interface