IBM CPC700, User Manual

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5-28 PCI Interface
The PCI command register is a 16-bit, read/write register used to control the operation of the PCI Bridge
on the PCI bus. Table 50. describes the bits.
Table 50.PCI Command Register Bits
Bit(s) Name Description
0 I/O Access Controls the CPC700’s response as a PCI I/O target.The CPC700
does not respond to I/O space accesses, therefore this bit is read-
only and always returns 0 when read.
1 Memory Access Controls the CPC700’s response as a PCI Memory target. A value of
1 enables the CPC700 to respond as a target. This bit is 0 (disabled)
at reset.
2 PCI Master Enable Enables the CPC700 to master cycles on the PCI bus. When this bit
is 0 (disabled), the CPC700 PCI interface responds as a PLB slave
only to accesses to PCICFGADR, PCICFGDATA, and the PCI Inter-
face Local Configuration Registers (PMMs and PTMs).
3 Special Cycle Enables special cycle operations. The CPC700 never monitors spe-
cial cycles, therefore this bit is read-only and returns 0 when read.
4 Mem Write & Invali-
date Enables memory write and invalidate command support. The
CPC700 does not generate this command, therefore this bit is read-
only and returns 0 when read
5 Palette Snooping Enables special palette snooping. The CPC700 is not a VGA device,
therefore this bit is read-only and returns 0 when read.
6 Parity Error
Response Parity error response. This bit enables the detection of all types of
PCI bus parity errors, including the following:
1) PCI data bus parity errors while PCI master
2) PCI data bus parity errors while PCI target
3) PCI address bus parity errors
When parity error response is disabled (set to 0) detection of these
errors is masked and PERR# is not asserted, although parity is still
generated.
7 Address Stepping Address stepping wait states. The CPC700 does not AD step (except
for address stepping when generating a Config Type 0 cycle), there-
fore this bit is read-only and returns 0 when read.
8 SERR# Enable Enable PCI_SERR#. Enables the assertion of PCI_SERR# when a
PCI bus parity error is detected when the CPC700 is a PCI target.
PCI command register bit 6 must also be enabled for address parity
errors. PCI command register bit 6 and Error Enable bit 1 must also
be enabled for write data parity errors.
9 Fast Back-to-Back Fast back-to-back write enable. This bit enables PCI masters to per-
form fast back-to-back transactions to different devices. the CPC700
does not perform fast back-to-back transactions, therefore this bit is
read-only and returns 0 when read.
15:10 Reserved These bits are reserved and return zeros when read.