IBM CPC700, User Manual

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4-4 Memory Controller
Detailed information regarding the memory controller registers can be found in Section 4.9, “Memory Con-
troller Register Description”.
4.4 Memory Access Arbiter
All accesses to main memory from the processor interface or the PCI interface are dispatched to the
SDRAM/ROM controller via the internal memory controller interface. The memory controller interface sup-
ports 1 full level of address pipelining for accesses to system memory which originate from single or multi-
ple sources. The possible sources for memory access requests which are broadcast onto the memory
controller interface are processor to memory, PCI to memory, and processor to memory write buffer. The
priority of the access request is determined by the processor interface bus arbiter and high priority write
buffer (W.B.) flush mechanism and is in descending order of priority: High Priority W.B. Flush, processor,
and PCI. The specific priority associated with processor and PCI requests is governed by a rotating token
associated with processor and PCI accesses. It is this priority that determines which transaction will be
broadcast onto the memory controller interface following the completion of the current access (if any is in
progress). A simple conceptual view of the priority associated with the routing of requests to the memory
controller interface is shown in Figure 9.
Figure 9. Routing of Memory Access Requests
All access requests are initiated to the memory controller as single doubleword, or double/quad double-
word (wrap address increment). For quad doubleword wrap address increment accesses, the doubleword
aligned address is incremented linearly to the end of the 32 byte aligned address boundary and wraps to
the beginning of the 32 byte aligned address transferring a four doubleword line.
4.5 SDRAM
The CPC700 memory controller supports both dual and quad internal bank SDRAMs in 32-bit and 64-bit
configurations (40-bit and 72-bit if using ECC) with fully programmable timing parameters. Both standard
and pipelined architecture SDRAMs are supported and the memory controller provides a mechanism to
enable/disable read and write with auto-precharge.
ECCERR 98 R/W ECC Error
RPB0P E0 R/W ROM / Peripheral Bank 0 Parameters
RPB1P E4 R/W ROM / Peripheral Bank 1 Parameters
RPB2P E8 R/W ROM / Peripheral Bank 2 Parameters
RPB3P EC R/W ROM / Peripheral Bank 3 Parameters
RPB4P F0 R/W ROM / Peripheral Bank 4 Parameters
Table 22. Offsets for Memory Controller Registers (Continued)
Register Offset R/W Description
Processor - Mem
PCI - Mem
Processor - Mem W.B.
Memory
Arbiter
High Priority
W.B. Flush
Controller
Interface