IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 3-5
3.5 Supported Processor Transfer Types
Based on signals TT[0:3] (see Table 7), the CPC700 responds to processor initiated transfers by generat-
ing a read transaction, a write transaction, or an address-only response. The CPC700 ignores TT[4] when
evaluating processor initiated transfers.
The CPC700 supports all processor to memory/PLB bursts and all single-beat transfer sizes and alignments
that do not cross a 4-byte boundary. The following table lists all supported processor transfer types and the
corresponding response from the CPC700.
NOTE: In Table 7, SBR is single-beat read and SBW is single-beat write.
Table 7. Supported Processor Transfer Type Encodings/Response
TT[0:3]
Processor
Operation Proc Bus
Transaction CPC700 Response for
Proc to Memory CPC700 Response for
Proc to PLB
0000 Clean block or lwarx Address only Assert AACK_N, No other response, No PLB
transaction
0001 Write with flush SBW or burst Memory write PLB write
0010 Flush block or stwcx Address only Assert AACK_N, No other response, No PLB
transaction
0011 Write with kill SBW or burst Memory write PLB write
0100 sync or tlbsync Address only Assert AACK_N, No other response
0101 Read or read with no
intent to cache SBR or burst Memory read PLB read
0110 Kill block or icbi Address only Assert AACK_N, No other response, No PLB
transaction
0111 Read with intent to
modify Burst Memory read PLB read
1000 eieio Address only Assert AACK_N, No other response
1001 Write with flush
atomic, stwcx SBW Memory write PLB write
1010 ecowx SBW Reserved
Assert AACK_N and TA_N. MCP_N asserted if
MCP_N assertion is enabled.
1011 Reserved Reserved
Assert AACK_N and TA_N. MCP_N asserted if
MCP_N assertion is enabled.