IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 14-5
14.1.4 CPR Registers
The following table lists the CPR registers. See Section 6.5, “CPR Registers” for detailed register informa-
tion.
14.1.5 PLB Macro Registers
PCIBUSNUM 40 R Bus Number
PCISUBBUSNUM 41 R Subordinate Bus Number
PCIDSCCNT 42 R Disconnect Counter
PCIARBCNTL 47 - 44 R/W PCI Arbiter Control
PCIERREN 48 R/W Error Enable
PCIERRSTS 49 R/W Error Status
PCIBRDGOPT1 4B - 4A R/W Bridge Options 1
SESR 4F - 4C R/W PLB Slave Error Syndrome Register
SEAR0 53 - 50 R PLB Slave Error Address Register 0
SEAR1 57 - 54 R PLB Slave Error Address Register 1
Reserved 5B - 58
Reserved 5F - 5C
PCIBRDGOPT2 61 - 60 R/W Bridge Options 2
Table 108. Clock, Power Management and Reset Control Registers
Register Address R/W Description
CPRPMCTRL FF50_0900 R/W Peripheral Power Management Control
CPRRESET FF50_0904 R/W Peripheral Reset Control
CPRCAPTEVNT FF50_0908 R/W GPT Capt Event Generation
CPRPLLACCESS FF50_090C R/W PLL Configuration Access Register - Unlocks CPRPLLTUNE
CPRPLLTUNE FF50_0910 R/W PLL Configuration Register (causes system reset upon write)
CPRSTRAPREAD FF50_0914 R Strapping Pin Status Read Register
Table 109. PLB Macro Configuration Registers
Register Address R/W Description
PACR FF50_085C R/W PLB Arbiter Control Register
PEAR FF50_0858 R/O PLB Error Address Register
PESR FF50_0850 R PLB Error Status Register (Read/Clear)
Table 107. PCI Configuration Register Offsets (Continued)
PCI Config Register Offset R/W Description