IBM CPC700, User Manual

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5-20 PCI Interface
For example, if it is desirable to put a value in the 32-bit register (see Figure 39.).
Figure 39.Little-Endian
Then Big-Endian software should either do a store (STW) of the value 44332211 or do a byte-reversed
store (STWBR) of the value 11223344. In either case, the following will appear on the appropriate word of
the 60X data bus (see Figure 40.).
Figure 40.Big-Endian
Note: The Little-Endian to Big-Endian conversion may also be accomplished through the use of the byte
swapping region registers of the CPC700’s processor interface. See Section 3.11 “Byte Swapping” and
Section 3.16.6 “PLBMIFOPT - PLB Master Interface Options” for information on using the CPC700’s byte
swapping capabilities.
5.9.1 PCI Interface Local Configuration Register Descriptions
These registers reside at hardcoded addresses in PLB space. They must be accessed using single beat
read or write cycles of the same size as shown in the register descriptions below. Failure to access all
bytes of a particular register could produce unexpected results. Reading of reserved bit locations will pro-
duce unpredictable values. Software must use appropriate masks to extract the desired bits. Writes must
preserve the values of reserved bit positions by first reading the register, merging the new value, and writ-
ing the result.
5.9.1.1 PMM 0 Local Address
PLB Address: FF40_0000h
Width: 32 bits
Reset Value: Undefined
Access Read/Write
This register defines the PLB starting address of range 0 in PLB space that is mapped to PCI Memory.
Only the bits that are ONE in the PMM 0 Mask are actually used to determine the starting address, all
other bits are don’t cares. Only bits 31:12 are writable; bits 11:0 are always zero.
31
0
MSB
LSB
Register Description:
11
22
33
44
0
31
MSB
LSB
Big Endian 60X
Data Bus Value:
44
33
22
11