IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 3-13
3.11 Byte Swapping
CPC700 includes support which is designed to ease the use of a Big Endian processor operating in a
Little-Endian system. This support includes the ability to swap bytes during read and write accesses to the
internal PLB bus from the processor. This mechanism can be used when accessing the PCI bus from the
processor. In addition CPC700 provides byte lane swapping from the PCI to/from memory in a fashion that
makes the otherwise Big-Endian memory look like Little-Endian memory from the PCI. Both of these
translations are disabled by default and may be enabled by programming the appropriate register bits.
Note: All accesses from the processor to system memory are handled as Big-Endian. No swapping mech-
anism is available for this data path.
3.11.1 Processor to PLB (PCI) Byte Swapping
Byte swapping can occur on the processor to PLB data path for both read and write cycles initiated by the
processor. With appropriate software/firmware support, and when enabled, this process allows the use of
a PowerPC processor in Big-Endian mode in a Little-Endian system. Up to three regions may be configured
to perform byte swapping by setting up the appropriate processor interface configuration registers (see Sec-
tion 3.16, “Processor Interface Register Description”):
• Starting Address(SA) per region (PLBMTLSAx registers)
• Ending Address (EA) per region (PLBMTLEAx registers)
• Enable bit per region (PLBMIFOPT register)
Byte swapping is performed between internal buffers in the processor interface as shown in Figure 4.
Figure 4. Processor to PLB Interface Translation Mechanism
32B
64
PLB
Processor
32
32
32B
8B
8B
Byte
•
Swapper
Byte
Swapper