IBM CPC700, User Manual

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8-10 IIC
or if none was present at the time the pending interrupt went to the on-deck state, the on-deck interrupt is
moved into the active state. Note that an active interrupt remains in the active state until it is cleared by the
program.
8.4.7 Lo Slave Address Register
When 7-bit addressing is to be used, the Lo slave address register needs to be written with this slave’s
address. The Hi slave address register is written with all zeros. For 7-bit addressing, bits 0:6 are used to
decode the address that was transmitted on the IIC bus; bit 7 is don’t care. When 10-bit addressing is
used, bits 0:7 are used to decode the second address byte that was transmitted on the IIC bus.
Table 87. Extended Status Register
Register ‘FF6X_0009’ - Extended Status
bit 0 IRQ pending. Set when an IRQ is still active, an IRQ is on-deck, and another interrupting
condition was generated. This bit might also be momentarily set while a new interrupting
condition moves from the pending to the on-deck state. When IRQ on-deck is set to a logic 0, a
pending IRQ will cause IRQ on-deck to be set back to a logic 1 and IRQ pending will be cleared
to a logic 0. The pending interrupt can be cleared by writing a logic 1 to this bit. If interrupts are
disabled, bit 5 in the mode control register is a logic 0, then this bit, IRQ pending, will not be set.
bit 1 Bus control state bit 0 (MSB). Read-only.
bit 2 Bus control state bit 1. Read-only.
bit 3 Bus control state bit 2 (LSB). Read-only.
bit 4 IRQ on-deck. Set when an IRQ is still active and another interrupting condition was generated.
This bit might also be momentarily set while a new interrupting condition moves from the on-
deck to the active state. When IRQ active is set to a logic 0, an on-deck IRQ will cause IRQ
active to be set back to a logic 1 and IRQ on-deck will be cleared to a logic 0. If there is a
pending IRQ, then IRQ on-deck will be set to a logic 1 on the next system clock. The on-deck
interrupt can be cleared by writing a logic 1 to this bit. If interrupts are disabled, bit 5 in the mode
control register is a logic 0, then this bit, IRQ on-deck, will not be set.
bit 5 Lost arbitration. Set to a logic 1 when a loss of arbitration has ended the requested master
transfer. If the requested operation was a write, then some bytes might not have been written. If
the requested operation was a read, then some bytes might not have been read. If the requested
operation used repeated start, then this master does not currently own the IIC bus.
bit 6 Incomplete transfer. When set to a logic 1, some of the bytes in the requested master transfer
were not sent or received from the slave. The transfer count register can be read to see how
many bytes were actually transferred.
bit 7 Transfer aborted. When set to a logic 1, a requested master transfer was aborted by a NOT
acknowledge during the transfer of the address byte. It is also set to a logic 1 when a requested
master transfer lost data because of the loss of arbitration during the transfer of the second or
greater data byte.
Table 88. Lo Slave Address Register
Register ‘FF6X_000A’ - Lo Slave Address
bit 0 Address bit 0 (MSB)
bit 1 Address bit 1
bit 2 Address bit 2
bit 3 Address bit 3
bit 4 Address bit 4
bit 5 Address bit 5
bit 6 Address bit 6 (LSB - 7 bit address)
bit 7 Address bit 7 (LSB - 10 bit address - D.C. for 7 bit))