IBM CPC700, User Manual

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2-2 Signal Descriptions
TT[0:4] High I/O Transfer Type: Indicates the type of the transfer currently in progress.
TSIZ[0:2] High I/O Transfer Size: Indicates the data transfer size for the current operation.
ARTRY_N Low I/O Address Retry: This signal is asserted by either the processor or the
CPC700 to indicate that the current address tenure needs to be rerun at
a later time.
TBST_N Low I/O Transfer Burst: Indicates a burst transfer of four 64-bit double-words on
the processor bus.
GBL_N Low I/O Global: This signal is asserted during snoop operations to indicate to
the processor that it must snoop the transaction.
TS_N Low I/O Transfer Start: Asserted low for one clock cycle to signal a valid
address on the A[0:31] lines. This signal is an input when the local
processor initiates a cycle on the bus and acts as an output when the
CPC700 initiates a snoop cycle on behalf of a PCI master access to
local memory.
BR_N Low I Bus Request: Processor bus request from the local processor.
BG_N Low O Bus Grant: Grant output indicating that the local processor may assume
mastership of the processor bus.
TA_N Low O Transfer Acknowledge: Indicates that a single-beat data transfer has
completed or that a data beat in a burst transfer completed successfully.
AACK_N Low O Address Acknowledge: Indicates that the address phase of a
transaction has completed.
DBG_N Low O Data Bus Grant: Indicates that the local processor may assume
mastership of the processor data bus.
MCP_N Low O Machine Check Pin: Indicates that an error condition has occurred and
that a machine check exception should be taken.
MCP_REQ High I Machine Check Interrupt Request: Input which may be used by an
external device to signal a machine check to the processor through the
MCP_N signal.
Signal Name
Active
Level
I / O Description