IBM CPC700, User Manual

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5-12 PCI Interface
memory read single-beat read PCI: DEVSEL_
PLB: request bus
PLB_M[x]Rearbi-
trate retry PCI
memory read line
or memory read
multiple word burst read
1
PCI: DEVSEL_
PLB: request bus
PLB_M[x]AddrAck transfer PCI burst
data
memory read line
or memory read
multiple word burst read
1
PCI: DEVSEL_
PLB: request bus
PLB_M[x]RdB-
Term Re-request PLB if
buffer becomes
half empty
memory read line
or memory read
multiple word burst read
1
PCI: DEVSEL_
PLB: request bus
PLB_M[x]Rearbi-
trate retry PCI
Read buffer hit on
memory read,
memory read line
or memory read
multiple n/a PCI: DEVSEL_
PLB: none
n/a source read data
to PCI. Request
PLB read
(prefetch) if read
multiple and buffer
becomes half
empty
memory write, sin-
gle-beat single-beat write,
1-4 byte
2
PCI: complete
transaction(post)
PLB: request bus
PLB_M[x]AddrAck
(of posted write
request) transfer data to
PLB
memory write, sin-
gle-beat single-beat write,
1-4 byte
2
PCI: complete
transaction(post)
PLB: request bus
PLB_M[x]Rearbi-
trate (of posted
write request) re-request PLB
memory write,
burst or memory
write and invali-
date word burst write
2,3
PCI: complete
transaction(post)
PLB: request bus
PLB_M[x]AddrAck
(of posted write
request) burst data to PLB
memory write,
burst or memory
write and invali-
date burst write
2,3
PCI: complete
transaction(post)
PLB: request bus
PLB_M[x]wrB-
Term increment buffer
address; re-
request PLB
memory write,
burst or memory
write and invali-
date burst write
2,3
PCI: complete
transaction(post)
PLB: request bus
PLB_M[x]Rearbi-
trate re-request PLB
Table 43.PCI Interface Responses to PCI Requests (Continued)
PCI Transaction PLB Size PCI, PLB Bus
Action PLB Response PCI Interface
Action