IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-39
4.7.1 ECC Registers
The ECC module uses
one configuration register to control its operation and another for error status.
After an ECC error has occurred, the ECC Error register must be reset in order to enable it to record future
errors. Reset this register with a write of all 1’s (x’FFFF_FFFF’). Detailed register information can be found
in Section 4.9.4, “ECC Specific Registers”.
The ECC Configuration register is used to configure the various modes of the ECC controller. If ECC is
implemented in a system, then the CPC700 will provide eight ECC bits and a single DQM output since all
memory transactions will be full 64-bit transfers (or 32-bit if 32-bit mode is selected). Write transactions of
less than the full data width will generate a read-modify-write cycle in order to generate ECC across the
entire data width.
In the event that the system is configured with a mixture of ECC and non-ECC banks, checking and correc-
tion must be disabled for all non-ECC banks. All memory transactions will also be the full bus width due to
the use of the single DQM in this situation. Partial writes will result in read-modify-write cycles to the non-
ECC memory banks.
Systems which do not require ECC protection may configure the CPC700 such that 8 DQM outputs are
available for SDRAM byte addressability for both read and write operations. This option is available via a
configuration strapping pin. See Section 6.4, “Power on Reset Pin Strapping Options” for details on how to
enable this mode.
Table 34. illustrates the relationship between the ECC enable and correction enable bits.
Mixed ECC/Non-ECC banks The ECC module supports banks 1-4, any or all of which
can be ECC enabled or disabled.
ECC is not used with bank 0 which must contain boot ROM
Bypass Mode The ECC module has a bypass mode in which ECC is not
performed on any transfers, and no extra clock cycles are
added to a memory transaction.
Checking and Correction Disable ECC error correction may be disabled on a per bank basis
to allow for non-ECC banks in a system that implements a
single DQM output.
Table 33. ECC Registers
Register
Symbol
Register Name
ECCCF ECC Configuration Register (bit 4, SD_WDTH, sets SDRAM bus width to 32 or 64-bit)
ECCERR ECC Error Register
Table 32. ECC Features (Continued)
Feature
Explanation