IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-43
4.9 Memory Controller Register Description
Memory controller registers are accessed through the MEMCFGADR and MEMCFGDATA registers. See
Section 4.3, “Memory Controller Registers” for additional information. To access one of the memory con-
troller configuration registers, write the appropriate index to register MEMCFGADR, then read the data
from or write the data to register MEMCFGDATA. All configuration accesses from the processor must be 4
Byte aligned, otherwise an error will be generated and the cycle not performed.
Note: In the tables of register field descriptions throughout this specification, some bits are shown shaded.
Those bits are reserved in the CPC700. Reading of reserved bits will produce unpredictable values. Soft-
ware must use appropriate masks to extract the desired bits. Writes must preserve the values of reserved
bit positions by first reading the register, merging the new values, and writing the result back.
4.9.1 Global Memory Configuration Registers
The following registers apply globally to the memory controller subsystem and are used to configure its
organization.
Register Address R/W Description
MEMCFGADR FF50_0008 R/W Memory Controller Configuration Address Register
MEMCFGDATA FF50_000C R/W Memory Controller Configuration Data Register