IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 5-45
set to 101b to indicate a Non-configured Bank Error, and MxRWS (Master x Read/Write Status) is set to 0
on a write, 1 on a read. No SEAR or SESR update is performed if either the Master Abort Error Enable bit
or the MErr Assertion Enable bit is not set.
5.10.3.3 PCI Target Abort Received While PCI Master
This error is generated when the CPC700’s PCI master receives a target abort while mastering a cycle on
the PCI bus. Upon detection of this error, the bridge PLB Slave may assert Sl[x]_MErr on the PLB bus in
response to this error, as explained below.
There are two masks associated with this event. The mask for PCI target abort error detection is register
48h, bit 6 (Error Enable Register, Target Abort Error Enable). If the error is detected, Sl[x]_MErr will be
asserted if register 48h, bit 2 (Error Enable Register, MErr Assertion Enable bit) is set to 1. For reads, the
bridge PLB slave will still complete the transfer on the PLB bus, driving the appropriate Sl[x]_MErr line for
each data beat. For posted writes, if this bit is set, the bridge PLB slave will assert Sl[x]_MErr for one cycle,
asynchronously to the actual corresponding write data beat on the PLB. For connected writes, Sl[x]_MErr
will be asserted with the data transfer and the data will be discarded. If Target Abort Error Enable is
cleared, the error is masked and Sl[x]_Merr is not asserted, regardless of the setting of MErr Assertion
Enable.
The following status bits are set:
1. If a target abort is received, register 06h, bit 12 (PCI Status Register, Target-Abort Detected bit) is set.
Setting of this bit is non-maskable. It can be reset by writing a 1 to it.
2. If a target abort is detected as an error, register 49h, bit 2 (Error Status Register, MErr Assertion Event
bit) is set to indicate an event which would cause Sl[x]_MErr to be asserted by the bridge PLB slave,
regardless of the setting of the MErr Assertion Enable bit. The MErr Assertion Event bit can be reset by
writing a 1 to it.
3. The PLB Slave Error Address Registers (SEAR’s) and the PLB Slave Error Syndrome Register are
updated as follows: The address of the aborted PCI request is saved in one of the SEAR registers (50h,
54h, 58h or 5Ch). SEARx is set if the MxAL field ((Master x Address Lock - x corresponding to the master
id of the PLB master whose read or write was master aborted) is cleared, meaning SEARx is unlocked. If
the MxFL (Master x Field Lock) field is cleared, the MxET (Master x Error Type) field of register 4Ch
(SESR) is set to 101b to indicate a Non-configured Bank Error, and MxRWS (Master x Read/Write Status)
is set to 0 on a write, 1 on a read. No SEAR or SESR update is performed if either the Target Abort Error
Enable bit or the MErr Assertion Enable bit is not set.
5.10.3.4 PCI Target Data Bus Parity Error Detection
This error is generated when the CPC700’s PCI target detects a data bus parity error on write data from a
PCI master doing a write cycle to PLB memory. PCI uses even parity.
This error can be masked by register 04h, bit 6 (PCI Command Register, PCI Parity Error Response bit).
The following status bits are set:
1. Register 06, bit 15 (PCI Status Register, Parity Error Detected bit) is set to indicate a PCI bus parity
error. Setting of this bit is non-maskable. It can be cleared by writing a 1 to it.
2. Register 06h, bit 14 (PCI Status Register, PCI_SERR# Asserted bit) is set if the mask at register 48h, bit
1 (Error Enable Register, Data Parity SERR_ Enable bit) is set to 1. The PCI_SERR# Asserted bit can be
cleared by writing a 1 to it.