8-8
IIC
8.4.5 Status Register
This register should be the first register read by an interrupt service or error handling routine. The status
will provide a summary of the state of the IIC interface and any previously requested master transfer. It can
also be read in a polling loop if the program is not going to use the IIC interrupts. The pending transfer and
error bits are the main indicators of the success or failure of the requested transfer. They can be decoded
as follows:
Pend=0, Error =0 - Requested transfer is complete, all data sent (received) to (from) slave.
Pend=0, Error =1 - Requested transfer is complete, not all data was transferred.
Pend=1, Error =0 - Requested transfer is not done, no errors detected.
Pend=1, Error =1 - Requested transfer is not done, an error was detected.
The program should wait for pending transfer to equal a logic 0 before any action is taken regarding master
transfers. If the error required the IIC interface to send a STOP, then bit 4 will also be set. Slave operations
can and should be serviced regardless of the state of a requested master transfer.
The program must clear this register before requesting another master transfer. The one exception is bit 0,
since it involves a slave transfer; it can be left set to a logic 1.
Bit 1 is the only writable bit in the IIC interface when the interface is in sleep mode.
After a master data buffer is read or written, time must be allowed to pass for bits 2 and 3 to be updated.
The actual amount of time is dependent upon the size of the access to or from the buffer. For double-byte
accesses, the status will be readable on the third system clock after the transfer. For byte accesses, the
status will be readable on the second system clock after the transfer.
Bits 0, 2, 3, 5, and 7 are read-only.
bit 6
Exit unknown IIC bus state. When set to a logic 1, the bus control state machine will exit the
unknown bus state, if IIC is currently in this state. If IIC is not in the unknown bus state, then
setting this bit to a logic 1 has no effect.
bit 7
Enable hold SCL. When set to a logic 1 and the slave is not ready, the IIC_SCL signal will be
held low by the slave until it becomes ready. When set to a logic 0 and the slave is not ready,
a not acknowledge is issued in response to a requested transfer on the IIC bus. This bit is
only relevant when the IIC interface is programmed as a slave.
Table 86. Status Register
Register ‘FF6X_0008’ - Status
bit 0
Slave status set. This bit is set whenever bits 0, 1, 2 or 3 are set in the extended control and
slave status register. It is provided as a summary of the slave status. This is a read-only bit.
bit 1
Sleep request. This bit is set to a logic 1 when sleep mode has been requested via the setting
of the IIC sleep init bit in the CPRPMCTRL register (see Section 6.5.1, “Peripheral Power
Management Control Register (CPRPMCTRL)” ). The bit will be cleared when either the IIC
interface is asleep and a start signal is detected on the IIC bus, or when the CPRPMCTRL IIC
sleep init bit is cleared.
bit 2
Master data buffer has data. When set to a logic1, the master data buffer has data in it. When
equal to a logic 0, the buffer is empty. This is a read-only bit.
bit 3
Master data buffer full. When set to a logic 1, the master data buffer is full. When equal to
logic 0, the master data buffer is not full. This is a read-only bit.
Table 85. Mode Control Register (Continued)
Register ‘FF6X_0007’ - Mode Control
Summary of Contents for CPC700
Page 10: ...Table of Contents x Table of Contents...
Page 16: ...Tables xvi List of Tables...
Page 28: ...1 12 CPC700 User s Manual Preliminary...
Page 72: ...3 36 Processor Interface...
Page 132: ...4 60 Memory Controller...
Page 184: ...5 52 PCI Interface...
Page 194: ...6 10 Clock Power Management and Reset...
Page 224: ...8 18 IIC...
Page 244: ...10 10 Interrupt Controller...
Page 246: ...I 11 2 JTAG...
Page 250: ...12 4 Processor Local Bus PLB...
Page 262: ...14 10 Register Summary...
Page 267: ...CPC700 User s Manual Preliminary...
