IBM CPC700, User Manual

Page: 208 / 268

8-2 IIC
Figure 47. 10-Bit Addressing
8.3 IIC Register Map
IIC registers are accessed via memory locations 0xFF6X_000Y, where X=2 for the IIC0 interface and X=3
for the IIC1 interface. Y designates the register within the IIC0 or IIC1 interface to be accessed.
The master data buffer is actually a 1-byte wide by 4-bytes deep first-in/first-out (FIFO) buffer. When a byte
is written to the master data buffer address, it goes into the fourth stage of the FIFO. If the third stage is
empty, the data just written into the fourth stage is moved into the third stage at the very next system clock.
This process is repeated for the second and first stages at each successive system clock. The byte will
move through the buffer until it bumps into a stage that has a valid byte of data. The data contained in this
buffer is either sent out onto the IIC bus when the IIC interface is performing a write operation, or is
received from the IIC bus when the IIC interface is performing a read operation.
Table 78. IIC Registers
Facility Name Mnemonic
CPC700
Map
Addres
s (hex)
Type
Affected by
Reset
Size
(bits)
Master Data Buffer IICxMDBUF FF6X_0000 0x0 R/W Yes- cleared 8,16
reserved Reserved FF6X_0001 0x1
Slave Data Buffer IICxSDBUF FF6X_0002 0x2 R/W Yes- cleared 8,16
reserved Reserved FF6X_0003 0x3
Lo Master Address IICxLMADR FF6X_0004 0x4 R/W No 8
Hi Master Address IICxHMADR FF6X_0005 0x5 R/W No 8
Control IICxCNTL FF6X_0006 0x6 R/W Yes- cleared 8
Mode Control IICxMDCNTL FF6X_0007 0x7 R/W Yes- cleared 8
Status IICxSTS FF6X_0008 0x8 R/W Yes- cleared 7
Extended Status IICxEXTSTS FF6X_0009 0x9 R/W Yes- cleared 8
Lo Slave Address IICxLSADR FF6X_000A 0xA R/W No 8
Hi Slave Address IICxHSADR FF6X_000B 0xB R/W No 8
Clock Divide IICxCLKDIV FF6X_000C 0xC R/W Yes- cleared 8
Interrupt Mask IICxINTRMSK FF6X_000D 0xD R/W Yes- cleared 8
Transfer Count IICxXFRCNT FF6X_000E 0xE R/W Yes- cleared 8
Extended Control and Slave
Status IICxXTCNTLSS FF6X_000F 0xF R/W Yes- cleared 8
Direct Control IICxDIRECTCNTL FF6X_0010 0x10 R/W Yes-set to ‘1’ 4
LSB MSB
X X X X X X X X
R/W
X X 0 1 1 1 1
Bit 0 Bit 15
10-bit address