IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 8-15
8.5 Interrupts
The IIC interface has two ways to handle the need for intervention. One way is for the processor to poll on
the pending transfer or slave status set bits in the status register. The second method is to use the IIC inter-
face’s interrupt capability. IIC interrupts are globally and specifically controlled via the enable interrupt bit in
the mode control register and the interrupt mask bits in the interrupt mask register. In addition, the shape of
the interrupt signal can be selected to be a pulse or a constant level by setting the enable pulsed IRQ bit in
the extended control and slave status register. The IIC hardware guarantees that the interrupt is activated
after the state of the logic has been set. This ensures that an interrupt service routine will read stable val-
ues from the IIC interface registers. All IIC interrupts are capable of triggering an interrupt request to the
CPC700’s interrupt controller. If enabled properly in the interrupt controller, an IIC interrupt can be used to
interrupt the processor. See Chapter 10., “Interrupt Controller” for additional information.
Since a master operation can have one interrupt and a slave operation can have two interrupts, the IIC
interface must respond to the case where up to three interrupts have been queued up. The current interrupt
is referred to as the active interrupt. The first interrupt in the queue is referred to as the on-deck interrupt,
while the second queued interrupt is called the pending interrupt. Multiple interrupts are held in the queue
until the active interrupt is cleared by writing a logic 1 to the IRQ active bit in the status register. Once the
active interrupt is cleared, the on-deck interrupt becomes the active interrupt and the pending interrupt
becomes the on-deck interrupt.
Any status associated with one of the multiple interrupts is immediately set into its corresponding register.
Thus, it is possible for an interrupt service routine to see the status for the current and the queued inter-
rupts. This can occur if, for example, the interrupt routine is itself interrupted prior to reading any status in
the IIC registers. If a second or third interrupt has occurred by the time the routine regains control, the sta-
tus seen at this time will include status associated with all three interrupting conditions. In this case, the
routine will not be able to determine which was the first interrupting condition. They will appear to have
been merged together. Note that if the interrupt service routine is intelligent enough to handle and clear all
conditions that are currently set in the status, as opposed to picking only one and servicing it, then the rou-
tine could see zero status for the subsequent interrupts.
A more typical situation involves the case where the interrupt routine has read the IIC status for the active
interrupt and a second on-deck interrupt occurs. In this case, the status has changed after it was first read
by the interrupt routine. Since status bits are cleared by writing a logic 1, no ill effects, such as lost status
information, result from this case. To illustrate, consider that the routine might have read 0x10 in the
Table 95. Direct Control Register
Register ‘FF6X_0010’ - Direct Control
bit 0 This bit is not used and will return 0 when read.
bit 1 This bit is not used and will return 0 when read.
bit 2 This bit is not used and will return 0 when read.
bit 3 This bit is not used and will return 0 when read.
bit 4 This bit is used to directly control the IIC_SDA output.
bit 5 This bit is used to directly control the IIC_SCL output.
bit 6 This bit is read-only. It is used to check the value of the SDA line on the IIC bus.
bit 7 This bit is read-only. It is used to check the value of the SCL line on the IIC bus.