IBM CPC700, User Manual

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14-2 Register Summary
14.1.2 Memory Controller Registers
The Memory controller registers are accessed similar to the processor interface registers through an indi-
rect address mechanism. The table below lists the indirect address and data registers for accessing the
memory controller.
The following table lists the offsets for the various configuration registers located within the memory con-
troller. See Section 4.9, “Memory Controller Register Description” for detailed register information.
BESRSET 44 W PLB Bus Error Syndrome Register Set (for test/verification
use)
Reserved 48
BEAR 4C R/W PLB Bus Master Error Address Register
Reserved 50
Reserved 54
PLBSWRINT 80 R/W Write Interrupt Region Base Address
Table 104. Memory Controller Register Addressing
Register Address R/W Description
MEMCFGADR FF50_0008 R/W Memory Controller Configuration Address Register
MEMCFGDATA FF50_000C R/W Memory Controller Configuration Data Register
Table 105. Offsets for Memory Controller Registers
Register Offset R/W Description
MCOPT1 20 R/W Memory Controller Options 1
MBEN 24 R/W Memory Bank Enable
MEMTYPE 28 R/W Installed Memory Type
RWD 2C R/W Bank Active Watchdog Timer
RTR 30 R/W Refresh Timer Register
DAM 34 R/W DRAM Addressing Mode
MB0SA 38 R/W Memory Bank 0 Starting Address
MB1SA 3C R/W Memory Bank 1 Starting Address
MB2SA 40 R/W Memory Bank 2 Starting Address
MB3SA 44 R/W Memory Bank 3 Starting Address
MB4SA 48 R/W Memory Bank 4 Starting Address
Table 103. Offsets for Processor Interface Registers (Continued)
Register Offset R/W Description