274
CHAPTER 8 16-bit reload timer
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Program Example in Event Counter Mode
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Processing specification
•
An interrupt is generated when rising edges of the pulse input to the external event input pin are counted
10000 times by the 16-bit reload timer/counter.
•
Operation is performed in the one-shot mode.
•
The rising edge is selected for the external trigger input.
•
EI
2
OS is not used.
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Coding example
;---------Interrupt program---------------------------------
WARI:
CLR I:UF0 ;Clear interrupt request flag
User processing
RETI ;Recovery from interrupt
CODE ENDS
;---------Vector setting------------------------------------
VECT CSEG ABS=0FFH
ORG 00FFB8H ;Setting vector to interrupt #17
DSL WARI
ORG 00FFDCH ;Reset vector setting
DSL START
DB 00H ;Setting to single chip mode
VECT ENDS
END START
ICR03 EQU 0000B3H
;For 16-bit reload timer
;Interrupt control register
TMCSR0 EQU 000066H ;Timer control status register
TMR0 EQU 003900H ;16-bit timer register
TMRLR0 EQU 003900H ;16-bit reload register
DDR2 EQU 000012H ;Port data register
UF0 EQU TMCSR0:2 ;Interrupt request flag bit
CNTE0 EQU TMCSR0:1 ;Counter operating enable bit
TRG0 EQU TMCSR0:0 ;Software trigger bit
;---------Main program-----------------------------------
CODE CSEG
; : ;Stack pointer (sp),already initialized
AND CCR,#0BFH ;Interrupt disabled
MOV I:ICR03,#00H ;Interrupt level 0 (strongesut)
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
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