Fujitsu F2MC-16LX Series, Hardware Manual

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CHAPTER 3 CPU
3.7 Clock
The clock generation section controls the internal clock that is an operating clock for
the CPU or resources. The clock generated by the clock generation section is called a
machine clock and one cycle of the machine clock is a machine cycle. The clock to be
supplied from a high-speed oscillator is called an oscillation clock and the 2- frequency
division of the oscillation clock is called a main clock. The 4-frequency division of a
clock to be supplied from a low-speed oscillator is called a sub clock and the clock to
be supplied from the PLL oscillator circuit is called a PLL clock.
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Clock
The clock generation section has oscillators and generates an oscillation clock by connecting an oscillator
to oscillation pins. External clocks that are input to the oscillation pins can be used as oscillation clocks.
The PLL clock multiplying circuit can be used to generate four clocks for multiplying the oscillation clock.
The clock generation section controls the oscillation stabilization wait time, PLL clock multiplying circuit,
and selects internal clock by the clock selector.
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Oscillation clock (HCLK)
This clock is generated by connecting an oscillator or inputting an external clock to the high-speed
oscillation pins (X0 and X1).
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Main clock (MCLK)
This clock is 2-frequency division of oscillation clock. It is an input clock to the timebase timer and clock
selector.
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Sub clock (SCLK)
This clock has a 4-frequency division of the clock generated by connecting an oscillator or inputting an
external clock to the low-speed oscillation pins (X0A and X1A). It can also be used as an operating clock
for the watch timer or as a low-speed machine clock.
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PLL clock (PCLK)
This clock is multiplied by the PLL clock multiplying circuit (PLL oscillator). It can be selected from four
types of clock according to the setting of the multiplication rate select bits (CKSCR: CS1, CS0).