46
CHAPTER 3 CPU
3.2.6
Direct page register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the
low address directly specified using the operand when executing the instruction by the
abbreviated direct addressing.
■
Direct page register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address
directly specified using the operand when executing the instruction by the abbreviated direct addressing.
The direct page register (DPR) is 8 bits long and is set to "01
H
" at a reset. It is a read and write register.
Figure 3.2-16 Generation of Physical Address in Direct Page Register (DPR)
Figure 3.2-17 shows the setting of direct page register (DPR) and an example of data access.
Figure 3.2-17 Setting of Direct Page Register (DPR) and Data Access Example
DTB register
DPR register
Direct addres during instruction
MSB
LSB
24bit
Physical address
A A A A A A A A
B B B B B B B B
C C C C C C C C
A A A A A A A A
B B B B B B B B
C C C C C C C C
bit24
bit16 bit15
bit8 bit7
bit0
MSB
Most significant bit
LSB
Least significant bit
MOV
S:56
H
#5A
H
DTB register
DPR resister
12
H
34
H
Upper 8bit Lower 8bit
5A
H
MSB
LSB
Result of executing instruction
123455
H
123457
H
123459
H
123454
H
123456
H
123458
H
MSB
Most significant bit
LSB
Least significant bit
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
Page 710: ......