Fujitsu F2MC-16LX Series, Hardware Manual

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113
CHAPTER 3 CPU
3.7.3 Clock select register (CKSCR)
The clock select register (CKSCR) is used to switch the clock mode between main
clock, subclock, and PLL clock and to select the oscillation stabilization wait time and
the PLL clock multiplier.
■
Clock select register (CKSCR)
Figure 3.7-4 Clock select register (CKSCR)
Reset value
1 1 1 1 1 1 0 0
B
12 13 11 10 9 8
14 15
: Reset value
: Read/Write R/W
: Read only R
: Oscillation clock HCLK
MCM
0
1
Operating in PLL clock
Operating in main clock or sub clock
PLL clock operation bit
bit14
SCM
0
1
Operating in sub clock
Operating in main clock or PLL clock
Sub clock operation bit
bit15
MCS
0
1
Select PLL clock
Select main clock
PLL clock select bit
bit10
SCS
0
1
Select sub clock
Select main clock
Sub clock select bit
bit11
R/W R/W R/W R/W R/W R/W R R
1
×
HCLK (4MHz)
2
×
HCLK (8MHz)
3
×
HCLK (12MHz)
4
×
HCLK (16MHz)
PSCCR: bit9
bit8
CS2 CS1
Multiplying select bit
Parenthesized values are examples calculated at an
oscillation clock frequency of 4 MHz.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
2
10
/HCLK (approx.256
µ
s)
2
13
/HCLK (approx.2.05ms)
2
14
/HCLK (approx.4.1ms)*
2
15
/HCLK (approx.8.19ms, other than power-on reset)*
2
16
/HCLK (approx.16.38ms, power-on reset only)*
bit13 bit12
WS1 WS0
Oscillation stabilization wait time select bit
Parenthesized values are examples calculated at an
oscillation clock frequency of 4 MHz.
0
0
1
1
0
1
0
1
*: When WS1/0="10" 2
15
/HCLK (appox.8.19ms) in MB90V495G
WS1/0="11" 2
17
/HCLK (appox.32.77ms, other than power-on reset)
2
18
/HCLK (appox.65.54ms, power-on reset only)
2
×
HCLK (8MHz)
4
×
HCLK (16MHz)
Unavailable
Unavailable
CS0
0
1
0
1
0
1
0
1