Fujitsu F2MC-16LX Series, Hardware Manual

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CHAPTER 16 CAN controller
Table 16.3-4 Function of the last event display register (LEIR)
Bit name Function
bit0
to
bit2
MBP2 to 0:
message buffer
pointer bit These bits indicate the number (x) of the message buffer where the last event
occurs which is corresponding to each message buffer pointer bit.
Receiving completed: Indicates number (x) of message buffer that completes
receiving message
Transmitting completed: Indicates number (x) of message buffer that completes
transmitting message
Node status transition: The values of the MBP2 to MBP0 bits are invalid.
When set to 0: The bit is cleared.
When the bit is set to 1: No effect.
Read using read modify write instructions: 1 always read
bit3,
bit4
undefined bit At a read: The value is undefined.
At a write: No effect.
bit5 RCE:
last event receiving
completed bit This bit indicates that receiving the last event is completed.
Receiving of last event completed: Sets bit to 1 when RCx bit in reception
complete register set (RCR: RCx = 1)
- Nothing is related to the setting of the reception complete interrupt
enable register (RIER).
- The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to 0: The bit is cleared.
When the bit is set to 1: No effect.
Read using read modify write instructions: 1 always read
bit6 TCE:
last event transmit-
ting completed bit This bit indicates that the transmitting the last event is completed.
Transmitting of last event completed: Sets bit to 1 when TCx bit in transmission
complete register set (TCR: TCx = 1)
- Nothing is related to the setting of the reception complete interrupt
enable register (TIER).
- The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to 0: The bit is cleared.
When the bit is set to 1: No effect.
Read using read modify write instructions: 1 always read
bit7 NTE:
last event node status
transmitting bit This bit indicates that the last event refers to the node status transition.
Last event referring to node status transition: Sets bit to 1 when NTx bit in
control status register set (CSR: NTx = 1)
- The NTE bit is set to 1 at the same time that the TCx in the
transmission complete register (TCR) is set.
- Nothing is related to the setting of the NIE bit in the control status
register (CSR).
When set to 0: The bit is cleared.
When the bit is set to 1: No effect.
Read using read modify write instructions: 1 always read
Note: When the last event indicate register (LEIR) is accessed in interrupt processing of the CAN
controller, the event causing the interrupt does not always match the event indicated by the
last event indicate register (LEIR). Other event may occur before the last event indicate
register (LEIR) is accessed in interrupt processing after an interrupt request is generated.