563
CHAPTER 17 Address Match Detecting Function
17.4
Explanation of Operation of Address Match Detection
Function
If the addresses of the instructions executed in the program match those set in the
detection address setting registers (PADR0 and PADR1), the address match detection
function will replace the first instruction with the INT9 instruction ("01
H
") and branch to
interrupt processing program.
■
Operation of Address Match Detection Function
Figure 17.4-1 shows the operation of the address match detection function when the detect addresses are set
and an address match is detected.
Figure 17.4-1 Operation of Address Match Detection Function
■
Setting Detect Address
1)Disable the detection address setting register 0 (PADR0) where the detect address is set for address
match detection (PACSR: AD0E = 0).
2)Set the detect address in the detection address setting register 0 (PADR0).
Set "FF
H
" at the higher bits
of the detection address setting register 0 (PADR0), "00
H
" at the middle bits, and "1F
H
" at the lower bits.
3)Enable the detect address setting register 0 (PADR0) where the detect address is set for address
match detection (PACSR: AD0E = 1).
■
Program Execution
4)If the address of the instruction to be executed in the program matches the set detect address, the
first instruction code at the matched address is replaced by the INT9 instruction code ("01
H
").
5)INT9 instruction is executed.
INT9 interrupt is generated and then interrupt processing program is
executed.
Address
FF001C:
FF001F:
FF0022:
Replaced by INT9(01
H
)
Instruction code
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0,#0000
A,#0000
A,#0880
Instruction address
executed in program
matches with detection
address setting register 0.
Program Execution
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
Page 710: ......