Fujitsu F2MC-16LX Series, Hardware Manual

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498
CHAPTER 16 CAN controller
Figure 16.3-13 Calculation Example of Bit Timing
(4) Condition of bit timing (BT) [BT
≥
8TQ]
(Unit:
µ
s)
MAchine clock (CLK)
4MHz (0.25
µ
s)
8MHz (0.125
µ
s)
16MHz (0.0625
µ
s)
2
1
0.5
4
2
1 6
3
1.5
8
4
2 10
5
2.5
12
6
3
14
7
3.5
16
8
4
18
9
4.5
20
10
5
22
11
5.5
24
12
6
26
13
6.5
28
14
7
30
15
7.5
8TQ
(Unit: Kbps)
TSEG1 + 1
1
667
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
2
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
3
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
100
4
333
286
250
222
200
182
167
154
143
133
125
118
111
105
100
95.2
5
286
250
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
6
250
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
7
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
8
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(3) Setting of resynchronous jump width (when resynchronous jump width is 4TQ)
(Unit: TQ)
(Unit: us) RSJ+1 (Division of TQ)
RSJW = (RSJ + 1)
×
TQ
1
0.5
2
1 3
1.5
4
2
(5) Condition of TSEG2
(Unit: TQ)
(Unit: TQ)
(Unit: us)
RSJW = (RSJ + 1)
×
TQ
TSEG2
≥
RSJW
TSEG2
≥
RSJW
1
1
0.5
2
2
1 3
3
1.5
4
4
2
(6) Condition of TSEG1
TSEG1
≥
Delay time + RSJW (Assuming that delaytime is 50ns)
×
2 + 4TQ
≥
5TQ
TSEG1
5 (Unit: TQ)
(2) Calculation of bit time (BT) based or the above setting and condition
BT = SY TSEG1 + TSEG2
= (1 + (TS1 + 1)+ (TS2+1))
×
TQ
= (3 + TS1 + TS2)
×
TQ
(1) (2) (3) (4) (5)
16
15
14
13
12 4
5
6
7
8
TSEG2 + 1 TSEG 1 + 1 SYNC_SEG
Sample
point
80%
75%
70%
65%
60%
Calculating of sample point
(1)
(2)
(3)
(4)
(5)
Sample point
Example : When 1TQ is 1/20 bit timing at 100Kbps (1/100Kbps/20)
Condition : (resynchronous jump width is 4TQ, delay time is 50
µ
s)
(1) Calculations of time quantum (TQ) [TQ = (PSC + 1)
×
CLK]
(Unit:
µ
s)
Machine clock (CLK)
4MHz (0.25
µ
s)
8MHz (0.125
µ
s)
16MHz (0.0625
µ
s)
1
0.25
0.13
0.06
2
0.5
0.25
0.13
3
0.75
0.38
0.19
4
1
0.5
0.25
5
1.25
0.63
0.31
6
1.5
0.75
0.38
7
1.75
0.88
0.44
8
2
1
0.5
9
2.25
1.13
0.56
10
2.5
1.25
0.63
11
2.75
1.38
0.69
12
3
1.5
0.75
13
3.25
1.63
0.81
14
3.5
1.75
0.88
15
3.75
1.88
0.94
Division of input clock (PSC+1)
SY (TSEG1 + 1) TSEG2 + 1
TSEG2 + 1