334
CHAPTER 12 DTP/external interrupt
12.3.1
DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
When a valid signal is input to the DTP/external interrupt pin or RX pin, the
corresponding interrupt request flag bit is set to "1".
■
DTP/external interrupt factor register (EIRR)
Figure 12.3-2 DTP/external interrupt factor register (EIRR)
Reset value
XXXXXXXX
B
12
13
11
10
9
8
bit15 to bit12,bit8
14
15
R/W : Read/Write
X : Undefined
- : Unused
R/W
-
-
-
R/W
R/W
R/W
R/W
0
1
ER7 to ER4,ER0
Without DTP/external interrupt
With DTP/external interrupt
Clear ER bit
No effection
DTP/external interrupt request flag bit
Read
Write
Table 12.3-2 Function of DTP/External Interrupt Factor Register (EIRR)
bit name
Function
bit8,
bit12
to
bit15
ER7 to ER4, ER0:
DTP/External interrupt
request flag bits
These bits are set to "1" when the edges or level signals set by the detection
condition select bits (ELVR: LB, LA) in the detection level setting register are input
to the DTP/external interrupt pin or RX pin.
When set to "1": When the DTP/external interrupt request enable bit (ENIR:
EN) is set to "1", an interrupt request is generated to the corresponding DTP/
external interrupt channel.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Note:
The bit returns "1" when read by a read modify write instruction.
If more than one DTP/external interrupt request is enabled (ENIR: EN = 1),
clear only the bit in the channel that accepts an interrupt (EIRR: ER = 0).No
other bits must be cleared unconditionally.
Reference:
When the (EI
2
OS) is started, the interrupt request flag bit is automatically
cleared after the completion of data transfer (EIRR: ER = 0)
bit9 to
bit11
Unused bits
Read: The value is undefined.
Write: No effect
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
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