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CHAPTER 16 CAN controller
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Starting receiving
To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register
(BVALR) to "1" and enable the message buffer (x).
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Canceling bus halt
After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
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Processing when receiving completed
•
If reception is successful after passing through the acceptance filter, the received message is stored in
the message buffer (x), "1" is set to the RCx of the reception complete register (RCR). For data frame
reception, RRTRx bit of the remote request receive register (RRTRR) is cleared to "0".For remote frame
reception, "1" is set to the RRTRx bit.
•
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt is generated.
•
Process the received message after checking the completion of receiving (RCR: RCx = 1).
•
Check the ROVRx bit in the receive overrun register (ROVRR) after the completion of processing the
received message.
- If the ROVRx bit is set to "0", the received message is enabled.When "0" is written to the RCx bit (a
reception complete interrupt is also cancelled), receiving is terminated.
- If the ROVRx bit is set to "1", a receive overrun occurs and the new message may overwrite the
received message.When a receive overrun occurs, write "0" to the ROVRx bit and then process the
received message again.
Above shows example of interrupt processing in the reception completion.
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
Page 710: ......