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CHAPTER 10 8/16-bit PPG timer
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Operation in 16-bit PPG output operation mode
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When either PPG0 pin output or PPG1 pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the
same pulse wave is output from both the PPG0 and PPG1 pins.
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When a reload value is set in the PPG reload register (PRLL0/PRLH0, PRLL1/PRLH1) and a PPG timer
operation is also enabled (PPGC0:PEN0=1 and PPGC1:PEN1=1), the PPG down counter starts count
operation as a 16 - bit down counter (PCNT0 + PCNT1).
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To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0).The count operation of the PPG down counter is
stopped and the output of the PPG output pin is held at a Low level.
•
If the PPG1 down counter underflows, the reload values set in the PPG0 and PPG1 reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded simultaneously to the PPG down counters (PCNT0 +
PCNT1).
•
When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGC0: PUF0 = 1, PPGC1: PUF1 = 1). If an interrupt request is enabled at either channel (PPGC0:
PIE0 = 1, PPGC1: PIE1 = 1), an interrupt request is generated.
Notes:
•
In the 16-bit PPG output operation mode, the underflow generation flag bits in the two
channels are set simultaneously when an underflow occurs (PPGC0: PUF0 = 1 and
PPGC1: PUF1 = 1).To prevent duplication of interrupt requests, disable either of the
underflow interrupt enable bits in the two channels (PPGC0: PIE0 = 0, PPGC1: PIE1 = 1
or PPGC0: PIE0 = 1, PPGC1: PIE1 = 0).
•
If the underflow generation flag bits in the two channels are set (PPGC0: PUF0 = 0 and
PPGC1: PUF1 = 0), clear the two channels at the same time.
Summary of Contents for F2MC-16LX Series
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...
Page 4: ......
Page 8: ...iv ...
Page 10: ...vi ...
Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...
Page 176: ...158 CHAPTER 3 CPU ...
Page 224: ...206 CHAPTER 5 Timebase timer ...
Page 294: ...276 CHAPTER 8 16 bit reload timer ...
Page 366: ...348 CHAPTER 12 DTP external interrupt ...
Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...
Page 446: ...428 CHAPTER 14 UART0 ...
Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...
Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...
Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...
Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...
Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...
Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...
Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...
Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...
Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...
Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...
Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...
Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...
Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...
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