Fujitsu F2MC-16LX Series, Hardware Manual, Page: 273 / 710

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CHAPTER 8 16-bit reload timer
8.3.1 Timer Control Status Registers (High) (TMCSR0: H,
TMCSR1: H)
The timer control status registers (High) (TMCSR0: H, TMCSR1: H) set the operation
mode and count clock.
This section also explains the bit 7 in the timer control status registers (Low) (TMCSR0:
L, TMCSR1: L).
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Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
Figure 8.3-3 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
MOD2 MOD1 MOD0
Operating mode select bit (internal clock mode)
(CSL1,0="00
B
","01
B
","10
B
")
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Input pin function
T : Machine cycle
12 13 11 10 9
8
bit9 bit8 bit7
MOD2 MOD1 MOD0
Operating mode select bit (Event count mode)
(CSL1,0="11
B
")
Rising edge
0
0
1
1
0
1
0
1
Input pin function Valid edge
bit9 bit8
bit7
CSL1 CSL0
Count clock select bit
Internal clock mode
2
1
T
2
3
T
2
5
T
0
0
1
1
0
1
0
1
Count clock Count clock cycle
bit11 bit10
14
Reset value
XXXX00000
B
: Undefined
: Reset value
X
: Read/Write R/W
R/W R/W R/W R/W R/W
7 15
: Unused
Event count mode External event clock
Falling edge
Both edge
Torigger input
Torigger input
Gate input
Torigger disabled
Rising edge
Falling edge
Both edge
"L" level
"H" level
Valid edge, level