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CHAPTER 19 512 KBIT FLASH MEMORY

19.7

Check the Execution State of Automatic Algorithm

Since the programming/erasing flow is controlled by the automatic algorithm, hardware
sequence flag can check the internal operating state inside of flash memory.

■

Hardware Sequence Flags

●

Overview of hardware sequence flag

The hardware sequence flag consists of the following 5-bit outputs:

•

Data polling flag (DQ7)

•

Toggle bit flag (DQ6)

•

Timing limit over flag (DQ5)

•

Sector erasing timer flag (DQ3)

•

Toggle bit 2 flag (DQ2)

These flags can be used to check completion of programming, chip and sector erasing, and

whether erase code writing are enabled.

The hardware sequence flags can be referred by setting command sequences and performing

read access to the address of a target sector in flash memory. The hardware sequence flag

should be output from the bank of only command published side.

"Bit Allocation of

Hardware Sequence Flags" gives the bit allocation of the hardware sequence flags.

•

To identify whether automatic programming/chip and sector erasing is in execution or

terminated, check the hardware sequence flag or the flash memory programming/erasing

status bit (FMCS: RDY) in the flash memory control status register. Programming/erasing is

terminated, returning to the read/reset state.

•

To create a programming/erasing program, use the DQ7, DQ6, DQ5, DQ3 and DQ2 flags to

check that automatic programming/erasing is terminated and read data.

•

The hardware sequence flags can also be used to check whether the second and later sector

erase code writing is enabled.

Table 19.7-1 Bit Allocation of Hardware Sequence Flags

Bit No.

7

6

5

4

3

2

1

0

Hardware sequence flag

DQ7

DQ6

DQ5

−

DQ3

DQ2

−

−

«
...
606
607
608
609
610
...
»

Summary of Contents for F2MC-16LX Series

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual CM44 10127 1E ...

Page 2: ......

Page 3: ...FUJITSU LIMITED F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual ...

Page 4: ......

Page 5: ...ed into ASICs application specific ICs and were developed as general purpose products in the F2 MC 16LX series This manual describes the functions and operation of the MB90895 series and is intended for engineers who intend to use MB90895 series microcontrollers to develop actual products Please read through this manual Trademarks F2MC an abbreviation for FUJITSU Flexible Microcontroller is a regi...

Page 6: ...xplains the functions and operation of the watch timer CHAPTER 10 8 16 bit PPG Timer This section describes the functions and operations of the 8 16 bit PPG timer CHAPTER 11 Delayed Interrupt Generation Module This section describes the functions and operations of the delayed interrupt generation module CHAPTER 12 DTP External Interrupt Circuit This section describes the functions and operations o...

Page 7: ...l Operation Flash This section describes the functions and operations of the dual operation flash CHAPTER 21 FLASH SERIAL PROGRAMMING CONNECTION EXAMPLE This section describes the functions and operations of the flash serial programming connection example APPENDIX The appendixes include an I O map pin function index interrupt vector index ...

Page 8: ...iv ...

Page 9: ...ed herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious...

Page 10: ...vi ...

Page 11: ...ral purpose Register 33 3 2 2 Accumulator A 34 3 2 3 Stack Pointer USP SSP 37 3 2 4 Processor status PS 40 3 2 5 Program counter PC 45 3 2 6 Direct page register DPR 46 3 2 7 Bank Register PCB DTB USB SSB and ADB 47 3 3 General purpose Register 48 3 4 Prefix Code 50 3 4 1 Bank select prefix PCB DTB ADB and SPB 51 3 4 2 Common register bank prefix CMR 53 3 4 3 Flag change inhibit prefix NCC 54 3 4 ...

Page 12: ...lect register CKSCR 113 3 7 4 PLL subclock control register PSCCR 116 3 7 5 Clock Mode 118 3 7 6 Oscillation Stabilization Wait Time 122 3 7 7 Connection of Oscillator and External Clock 123 3 8 Low power Consumption Mode 124 3 8 1 Block Diagram of Low power Consumption Circuit 127 3 8 2 Registers for Setting Low power Consumption Modes 129 3 8 3 Low power consumption mode control register LPMCR 1...

Page 13: ...8 6 2 Configuration of Watchdog Timer 209 6 3 Watchdog Timer Registers 211 6 3 1 Watchdog timer control register WDTC 212 6 4 Explanation of Operations of Watchdog Timer Functions 214 6 5 Precautions when Using Watchdog Timer 217 6 6 Program Examples of Watchdog Timer 218 CHAPTER 7 16 bit I O timer 219 7 1 Overview of 16 bit Input Output Timer 220 7 2 Block Diagram of 16 bit Input Output Timer 221...

Page 14: ...h Timer 288 CHAPTER 10 8 16 bit PPG timer 289 10 1 Overview of 8 16 bit PPG Timer 290 10 2 Block Diagram of 8 16 bit PPG Timer 293 10 2 1 Block Diagram for 8 16 bit PPG Timer 0 294 10 2 2 Block Diagram of 8 16 bit PPG Timer 1 296 10 3 Configuration of 8 16 bit PPG Timer 299 10 3 1 PPG0 Operation Mode Control Register PPGC0 301 10 3 2 PPG1 Operation Mode Control Register PPGC1 303 10 3 3 PPG0 1 cou...

Page 15: ...it A D Converter 354 13 3 1 A D Control Status Register High ADCS H 356 13 3 2 A D Control Status Register Low ADCS L 359 13 3 3 A D Data Register High ADCR H 362 13 3 4 A D Data Register Low ADCR L 364 13 3 5 Analog input enable register ADER 365 13 4 Interrupt of 8 10 bit A D Converter 367 13 5 Explanation of Operation of 8 10 bit A D Converter 368 13 5 1 Single shot conversion mode 369 13 5 2 C...

Page 16: ... 446 15 4 Interrupt of UART1 448 15 4 1 Generation of Receive Interrupt and Timing of Flag Set 450 15 4 2 Generation of Transmit Interrupt and Timing of Flag Set 452 15 5 UART1 Baud Rate 453 15 5 1 Baud rate by dedicated baud rate generator 455 15 5 2 Baud Rate by Internal Timer 16 bit Reload Timer 458 15 5 3 Baud rate by external clock 460 15 6 Explanation of Operation of UART1 461 15 6 1 Operati...

Page 17: ...CAN Controller 552 16 7 Program Example of CAN Controller 553 CHAPTER 17 Address Match Detecting Function 555 17 1 Overview of Address Match Detection Function 556 17 2 Block Diagram of Address Match Detection Function 557 17 3 Configuration of Address Match Detection Function 558 17 3 1 Address detection control register PACSR 559 17 3 2 Detect address setting registers PADR0 PADR1 561 17 4 Expla...

Page 18: ... 5 Sector Erase Suspension 606 19 8 6 Sector Erase Resumption 607 CHAPTER 20 DUAL OPERATION FLASH 609 20 1 Overview of Dual Operation Flash 610 20 2 Register for Dual Operation Flash 611 20 3 Operation of Dual Operation Flash 613 APPENDIX 615 APPENDIX A Instructions 616 A 1 Instruction Types 617 A 2 Addressing 618 A 3 Direct Addressing 620 A 4 Indirect Addressing 627 A 5 Execution Cycle Count 634 ...

Page 19: ...s the features and basic specifications of MB90895 series 1 1 Features of the MB90895 series 1 2 Product Lineup for MB90895 Series 1 3 Block Diagram of MB90895 Series 1 4 Pin Assignment 1 5 Package Dimensions 1 6 Pin Description 1 7 I O Circuit ...

Page 20: ...lock selectable from 1 2 frequency of oscillation clock or 1 to 4 multiples of oscillation clock 4 MHz to 16 MHz when oscillation clock is 4 MHz Sub clock operation 8 192 kHz MB90F897 Minimum instruction execution time 62 5 ns 4 MHz oscillation clock 4 multiplied PLL clock 16 MB CPU memory space Internal 24 bit addressing Instruction system optimized for controllers Various data types bit byte wor...

Page 21: ...apture ICU 4 channels By detecting the edge of the pin input the count value of the 16 bit free run timer is latched to generate an interrupt request CAN Controller 1 channel Conforms to CAN Specification Ver 2 0A and Ver 2 0B Built in 8 message buffers Transfer rate 10 Kbps to 1 Mbps at 16 MHz machine clock frequency CAN wake up UART0 SCI UART1 SCI 2 channel Full duplex double buffer Clock asynch...

Page 22: ... S Classification Evaluation product Flash ROM ROM Size 64 KB RAM Size 6 KB 2 KB Clock Dual line model MB90F897 Dual line model MB90F897S Single line model Process CMOS Package PGA256 LQFP 48 with 0 50 mm pin pitch Operating supply voltage 4 5V to 5 5V 3 5V to 5 5V Power supply for emulator Not provided Setting of DIP Switch S2 when using emulation pod MB2145 507 For details refer to the MB2145 50...

Page 23: ...75ms Assuming an oscillation clock frequency of 4 MHz 16 bit I O timer 16 bit free run timer Channel count 1 interrupt by overflow generation Input capture Channel count 4 Free run timer value held at pin input timing rising edge falling edge both edges 16 bit reload timer 1 Channel count 2 16 bit reload timer operation Count Clock Cycle 0 25µs 0 5µs 2 0µs Assuming a machine clock frequency of 16 ...

Page 24: ...T0 SCI Channel count 1 Clock synchronous transfer 62 5 K bps to 2 M bps Clock asynchronous transfer 1 202 bps to 62 500 K bps Two way serial communication function master slave connected communication UART1 SCI Channel count 1 Clock synchronous transfer 62 5 K bps to 2 M bps Clock asynchronous transfer 9 615 bps to 500 K bps Two way serial communication function master slave connected communicatio...

Page 25: ... F2MC 16LX core Clock controller Watch timer Timebase timer 8 10 bit A D converter 8ch IN0 to IN3 RAM Prescaler FLASH INT4 to INT7 RX TX PPG0 to PPG3 TIN0 TIN1 TOT0 TOT1 X0A X1A RST X0 X1 SCK0 SOT0 SIN0 AVcc AN0 to AN7 AVss AVR ADTG UART0 Prescaler SCK1 SOT1 SIN1 UART1 16 bit PPG timer 2ch CAN DTP external interrupt 16 bit reload timer 2ch 16 bit free run timer Input capture 4ch Internal data bus ...

Page 26: ...19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 34 36 48 47 46 45 44 43 42 41 40 39 38 37 P56 AN6 P16 PPG2 P17 PPG3 P37 ADTG P50 AN0 P51 AN1 P52 AN2 P53 AN3 AVR AVCC AV SS MD 0 RST MD 1 MD 2 X0 X1 V CC VSS C X0A P35 X1A P36 P40 SIN1 P41 SCK1 P42 SOT1 P30 SOT0 P31 SCK0 P32 SIN0 P10 IN0 P11 IN1 P12 IN2 P13 IN3 P14 PPG0 P15 PPG1 P20 TINO P21 TOT0 P22 TIN1 P23 TOT1 P24 INT4 P25 INT5 P26 INT6 P27 INT7 ...

Page 27: ...FP32 7 7 0 50 48 pin plastic LQFP FPT 48P M26 Note 1 These dimensions include resin protrusion Note 2 Pins width and pins thickness include plating thickness Note 3 Pins width do not include tie bar cutting remainder FPT 48P M26 C 2003 FUJITSU LIMITED F48040S c 2 2 24 13 36 25 48 37 INDEX SQ 9 00 0 20 354 008 SQ 0 145 0 055 006 002 0 08 003 A 0 8 059 004 008 0 10 0 20 1 50 0 60 0 15 024 006 0 10 0...

Page 28: ...t TIN0 Event input pin for reload timer 0 This pin should be set to input port 13 P21 D General purpose I O port TOT0 Event output pin for reload timer 0 This pin is enabled only when the output setting is enabled 14 P22 D General purpose I O port TIN1 Event input pin for reload timer 1 This pin should be set to input port 15 P23 D General purpose I O port TOT1 Event output pin for reload timer 1 ...

Page 29: ...etting of the UART1 is enabled 39 P42 D General purpose I O port SOT1 Serial data output pin for UART1 This pin functions only when the serial data output setting of the UART1 is enabled 40 P43 D General purpose I O port TX CAN transmission output pin This pin is enabled only when the output setting is enabled 41 P44 D General purpose I O port RX CAN reception input pin This pin should be set to i...

Page 30: ...A Low speed oscillation pin P36 D General purpose I O port 48 AVSS VSS power input pin for A D converter MB90F897 X1A X0A MB90F897S P36 P35 Table 1 6 1 Pin Description 3 3 Pin Number Pin Name Circuit Type Functional description M26 ...

Page 31: ...r Oscillation feedback resistor for low speed approximately 10MΩ B Hysteresis input with pull up resistor pull up resistor about 50kΩ C Hysteresis input D CMOS hysteresis input CMOS level output Standby control provided Automotive Input X1 X1A X0 X0A Standby control signal Clock input Hysteresis input R Vcc R Hysteresis input R Standby control R Digital output Digital output Hysteresis input Pch N...

Page 32: ...provided Automotive Input H CMOS hysteresis input CMOS level output Standby control provided CMOS input Automotive Input Table 1 7 1 I O Circuit 2 2 Classifi cation Circuit Remarks Standby control R Digital output Digital output Hysteresis input Pch Nch Vcc Vss R automotive input Analog input Hysteresis input Vss R R Standby control R High current output High current output Hysteresis input Pch Nc...

Page 33: ...15 CHAPTER 2 HANDLING DEVICES This chapter describes the precautions when handling the general purpose one chip micro controller 2 1 Precautions when Handling Devices ...

Page 34: ...ing un used pins If unused input pins remain open a malfunction or latch up may cause permanent damage so take countermeasures such as pull up or pull down using a 2 kΩ or larger resistor Leave unused input pins open in the output state or if left in the input state treat them in the same manner as for input pins in use Precautions when using external clock When an external clock is used drive onl...

Page 35: ...operation the PC board is recommended to have the artwork with the X0 and X1 pins enclosed by a ground line Procedure of A D converter analog input power on Always apply power to the A D converter power and the analog input AN0 to AN7 pins after or concurrently with the digital power VCC on Always turn off the A D converter power and the analog input before or concurrently with the digital power d...

Page 36: ...18 CHAPTER 2 HANDLING DEVICES ...

Page 37: ...s chapter explains the CPU functions of the MB90895 series 3 1 Memory Space 3 2 Dedicated Registers 3 3 General purpose Register 3 4 Prefix Code 3 5 Interrupt 3 6 Reset 3 7 Clock 3 8 Low power Consumption Mode 3 9 CPU Mode ...

Page 38: ... Example of Relationships between F2MC 16LX System and Memory Map Data Interrupt Peripheral circuit General purpose ports 1 F2 MC 16LX CPU F2MC 16LX device EI2OS 1 The capacity of the internal RAM depends on the product 2 The capacity of the internal ROM depends on the product FFFFFFH 010000H FE0000H 004000H 003900H 000900H 000380H 000180H 000100H 000020H 0000B0H 0000C0H 000000H Data area EI2 OS d...

Page 39: ...o be used as ordinary RAM When this area is used as general purpose registers they can be accessed quickly using a short instruction through general purpose register addressing Expanded intelligent I O service EI2OS descriptor area address 000100H to 00017FH This area holds the transfer mode I O address transfer count and buffer address This area is allocated to part of the RAM area and can also b...

Page 40: ...when the ROM mirroring function is enabled and disabled Figure 3 1 2 Memory Map for MB90895 Series When ROM mirroring function is enabled Address 1 internal access memory Access prohibited Products Address 1 MB90V495G MB90F897 S In MB90F897 S When the area of FE0000H to FEFFFFH is read data of FF0000H to FFFFFFH can be read FFE000H FFFFFFH FE0000H 010000H 003900H 000100H 0000C0H 000000H 001900H 00...

Page 41: ... addresses of the 00 bank so the table in ROM can be referenced without specifying far with a pointer For example if 00C000 H is accessed data in ROM at FFC000 H is actually accessed However the ROM area in the FF bank exceeds 48 KB and all areas cannot be seen as images in the 00 bank Therefore ROM data from FF4000H to FFFFFFH is see as an image from 004000H to 00FFFFH so the ROM data table shoul...

Page 42: ...an image in the 00 bank in MB90F897 S and MB90V495G 3 In MB90F897 S when FE Bank is read FF Bank can be read FFFFFFH FC0000H 010000H 003800H 002000H 001900H 000100H 000000H 000900H RAM FFFFFFH FFE000H FF0000H FE0000H 010000H 004000H 000100H 000000H 003900H 0000C0H 0000C0H Extended I O area Single chip ROM area 2 Image in the FF Bank I O ROM Single chip Internal ROM external bus External ROM extern...

Page 43: ...g The bank addressing is to access the 16 MB memory space which divided into 256 64 KB banks by specifying banks and addresses in banks Figure 3 1 4 Memory Management in Linear and Bank Types shows overview of memory management in linear and bank type Figure 3 1 4 Memory Management in Linear and Bank Types Linear types bank types 00 Bank 01 Bank 02 Bank 64KByte 12 Bank FD Bank FE Bank FF Bank Divi...

Page 44: ...t Physical Direct Addressing in Linear Type Addressing by Indirect specifying 32 bit Register Figure 3 1 6 Example of indirect specifying 32 bit General purpose Register in Linear Type Old program bank Program counter New program bank Program counter 10 12 452D 3456 JMPP 123456H JMPP 123456H Next instruction 10452DH 123456H MOV A RL1 7 Old accumulator New accumulator XXXX 003A 3AH FFFF06F9H RL1 Up...

Page 45: ...se of it Table 3 1 1 Access Space for Each Bank Register and Major Use of Access Space Bank Register Name Access Space Major Use Reset Value Program bank register PCB Program PC space Stores instruction code vector tables immediate data FFH Data bank register DTB Data DT space Stores data that can be read written and can access resource control registers and data registers 00H User stack bank regi...

Page 46: ... Note For details see 3 2 Dedicated Registers Program space Additional space User stack space Data space System stack space FFH 0FH 0DH 0BH 07H PCB Program bank register ADB Additional bank register USB User stack bank register DTB Data bank register SSB System stack bank register FFFFFFH FF0000H 0FFFFFH 0F0000H 0DFFFFH 0D0000H 0BFFFFH 0B0000H 07FFFFH 070000H 000000H Physical address Table 3 1 2 A...

Page 47: ... the order in which multi byte data is stored Lower 8 bits are allocated to n address and in order of n 1 n 2 n 3 and Figure 3 1 8 Store of Multi byte Data in RAM Storage of Multi byte Length Operand Figure 3 1 9 Storage of Multi byte Operand shows the configuration of a multi byte length operand in memory Figure 3 1 9 Storage of Multi byte Operand 01010101B 11001100B 11111111B 00010100B n address...

Page 48: ...accesses multi byte data the address after the FFFFH address is the 0000H address of the same bank Figure 3 1 11 Access to Multi byte Data on Bank Boundary shows an example of access instruction for multi byte data on the bank boundary Figure 3 1 11 Access to Multi byte Data on Bank Boundary Lower address Upper address 35H A4H F0H PUSHW RW1 RW3 35A4H 6DF0H 6DH PUSHW RW1 RW3 SP RW1 35A4H RW3 6DF0H ...

Page 49: ... It is a 16 bit pointer for user stack address System stack pointer SSP It is a 16 bit pointer for system stack address Processor status PS It is a 16 bit register for system status Program counter PC It is a 16 bit register for stored position of current instruction Program bank register PCB It is a 8 bit register for program space Data bank register DTB It is a 8 bit register for data space User...

Page 50: ...CH and FFFFDH Direct page register DPR 01H Program bank register PCB Value of reset vector data at FFFFDEH Data bank register DTB 00H User stack bank register USB 00H System stack bank register SSB 00H Additional data bank register ADB 00H ILM RP CCR PS bit15 bit13 bit12 bit8 bit7 bit0 0 0 0 0 0 0 0 0 0 1 x x x x x Note The above reset values are the reset values for the device The reset values fo...

Page 51: ...h the dedicated registers these registers can be used for addressing and the use of these registers is not limited Figure 3 2 2 Dedicated Registers and General purpose Register shows the allocation of the dedicated registers and the general purpose registers Figure 3 2 2 Dedicated Registers and General purpose Register Accumulator User stack pointer System stack pointer Processor status Program co...

Page 52: ...function When data of word length or less is transferred to the AL register data stored in the AL register is transferred automatically to the AH register Code extended function and zero extended function When transferring data of byte length or less to the AL register the data is code extended MOVX instruction or zero extended MOV instruction to be the 16 bit length and stored in the AL register ...

Page 53: ... 5 Example of 8 bit Data Transfer to Accumulator A Data Saving Zero extended MOVW A 3000H Before execution XXXXH 2456H DTB B5H After execution 2456H 7788H AH AL 77H 88H MSB LSB Memory space Instruction of storing 3000H address data in registers B53001H B53000H X Undefined MSB Most significant bit LSB Least significant bit DTB Data bank register MOV A 3000H XXXXH 2456H DTB B5H 2456H 0088H AH AL 77H...

Page 54: ...6 8FH 74H 2BH 52H A6153FH A61541H A6153EH A61540H Before execution After execution Memory space X Undefined MSB Most significant bit LSB Least significant bit DTB Data bank register MOVL A RW1 6 8F74H 2B52H MSB LSB 15H 38H RW1 6 XXXXH XXXXH DTB A6H AH AL 8FH 74H 2BH 52H A6153FH A61541H A6153EH A61540H Before execution After execution Memory space X Undefined MSB Most significant bit LSB Least sign...

Page 55: ...er stack The addresses of the stack pointers are set by the stack flag of the condition code register CCR S as shown in Table 3 2 2 Stack Address Specification Since the stack flag CCR S is set to 1 by a reset the system stack pointer is used after reset Ordinarily the system stack pointer is used in processing the stack at the interrupt routine and the user stack pointer is used in processing the...

Page 56: ...USHW A when S flag is 0 PUSHW A when S flag is 1 AL 0 USB USP S flag SSB SSP XXH XXH C6H F328H A624H 56H 1234H MSB LSB AL 0 USB USP S flag SSB SSP A6H C6H F326H A624H 56H 1234H 24H Because S flug 0 use the user stack pointer AL 1 USB USP S flag SSB SSP XXH XXH C6H F328H A624H 56H 1234H MSB LSB AL 1 USB USP S flag SSB SSP A6H C6H F328H A624H 56H 1232H 24H Because S flug 1 use the system stack point...

Page 57: ... even though the user stack area is being used it is forced to be switched to the system stack area Therefore in systems mainly using the user stack area also the system stack area must be set correctly In particular only the system stack area should be used unless it is necessary to divide the stack space Notes As a general rule even addresses should be set in the stack pointers SSP and USP The s...

Page 58: ... CPU is currently accepting The value of this register is compared to the value of the interrupt level setting bits of the interrupt control register ICR IL0 to IL2 corresponding to the interrupt request of each resource Register bank pointer RP This register set the memory block register bank to be used for the general purpose registers allocated in the internal RAM General purpose registers can ...

Page 59: ... stack processing When the stack flag CCR S is 0 the user stack pointer USP is enabled When the stack flag CCR S is 1 the system stack pointer SSP is enabled If an interrupt is accepted or a reset occurs the flag is set to 1 Sticky bit flag T This flag is set to 1 if any of the items of data shifted out by a carry is 1 when the logic right shift instruction or arithmetic right shift instruction is...

Page 60: ...c value at the execution of operation this flag is set to 1 If no overflow occurs the flag is cleared to 0 Carry flag C If a carry from the MSB or to the least significant bit LSB occurs at the execution of operation this flag is set to 1 If no carry occurs this flag is cleared to 0 Note For the state of the condition code register CCR during instruction execution refer to the Programming Manual ...

Page 61: ...e shown in Figure 3 2 13 Physical Address Conversion Rules in General purpose Register Area Figure 3 2 13 Physical Address Conversion Rules in General purpose Register Area The register bank pointer RP can take the values from 00H to 1FH so that the starting address of the register bank can be set within the range of 000180H to 00037FH The assembler instruction can use the 8 bit immediate value tr...

Page 62: ...ed with an interrupt enabled CCR I 1 When an interrupt is accepted its interrupt level value is set in the interrupt level mask register ILM Thereafter an interrupt with a level value lower than the set level value is not accepted At a reset the interrupt level mask register ILM is always set to 0 to enter the interrupt disabled highest interrupt level state The assembler instruction can use the 8...

Page 63: ... lower 16 bits As shown in Figure 3 2 15 Program counter PC the actual addresses are combined into 24 bits The program counter PC is updated by the execution of the conditional branch instruction the subroutine call instruction by an interrupt or reset etc The program counter PC can also be used as the base pointer when reading the operand Figure 3 2 15 Program counter PC PCB PC FEH ABCDH Upper 8 ...

Page 64: ...eset It is a read and write register Figure 3 2 16 Generation of Physical Address in Direct Page Register DPR Figure 3 2 17 shows the setting of direct page register DPR and an example of data access Figure 3 2 17 Setting of Direct Page Register DPR and Data Access Example DTB register DPR register Direct addres during instruction MSB LSB 24bit Physical address A A A A A A A A B B B B B B B B C C ...

Page 65: ...e 16 MB space at executing a software interrupt instruction or at a hardware interrupt or exception interrupt Data bank register DTB The data bank register DTB sets the data DT space User Stack Bank Register USB and System Stack Bank Register SSB The user stack bank register USB and system stack bank register SSB set the stack SP space The bank register that is used is determined by the value of t...

Page 66: ...general purpose register 000180H RP x 10H Figure 3 3 1 shows the allocation and configuration of the general purpose register banks in memory space Figure 3 3 1 Allocation and Configuration of General Purpose Register Banks in Memory Space Note The register bank pointer RP is initialized to 00000B by a reset Internal RAM Register bank 31 Register bank 30 Register bank 21 Register bank 20 Register ...

Page 67: ...hanged by a reset meaning that the state before the reset is held However at power on the value is undefined Table 3 3 1 shows the typical functions of the general purpose register Table 3 3 1 Typical Functions of the General purpose Register Register Name Function R0 to R7 Used as operands for various instructions Note R0 can also be used as the barrel shift counter or the normalized instruction ...

Page 68: ...uction can be selected regardless of the addressing types Common register bank prefix CMR When the common register bank prefix CMR code precedes an instruction for accessing a general purpose register the general purpose register to be accessed by the instruction can be changed to a common bank register bank selected when the register bank pointer RP is 0 at 000180H to 00018FH regardless of the cu...

Page 69: ...ce PCB Program space DTB Data space ADB Additional space SPB When the stack flag CCR S is 0 user stack space is selected When the stack flag is 1 system stack space is selected Table 3 4 2 Instructions Unaffected by Bank Select Prefix Instruction Types Instruction Effect of bank select prefix code String instruction MOVS SCEQ FILS MOVSW SCWEQ FILSW The bank register specified for the operand is us...

Page 70: ...n Description Flag change instruction AND CCR imm8 OR CCR imm8 The bank select prefix code affects up to the next instruction ILM setting instruction MOV ILM imm8 The bank select prefix code affects up to the next instruction PS Return instruction POPW PS Do not add the bank select prefix code to the PS return instruction ...

Page 71: ...mon register bank prefix CMR code precedes an instruction for accessing a general purpose register the general purpose register to be accessed by the instruction can be changed to a common bank register bank selected when the register bank pointer RP is 0 at 000180H to 00018FH regardless of the current value of the register bank pointer RP Table 3 4 4 shows the instructions requiring care when usi...

Page 72: ...nge Inhibit Prefix NCC Instruction Types Instruction Description String instruction MOVS SCEQ FILS MOVSW SCWEQ FILSW Do not the add the NCC code to the string instruction Flag change instruction AND CCR imm8 OR CCR imm8 The CCR changes by execution of an instruction regardless of the presence or absence of the NCC code The flag change inhibit prefix code affects the next instruction PS Return inst...

Page 73: ...as shown below Interrupt Inhibition Even if generated an interrupt request is not accepted during execution of a prefix code and interrupt inhibit instruction The interrupt is processed when any other instruction is executed after execution of a prefix code or interrupt inhibit instruction Figure 3 4 1 Interrupt Inhibition Table 3 4 6 Prefix Code and Interrupt Inhibit Instruction Prefix Code Inter...

Page 74: ...tion Figure 3 4 2 Interrupt Inhibit Instruction and Prefix Code Array of Prefix Codes For a succession of conflicting prefix codes PCB ADB DTB SPB the last one is enabled Figure 3 4 3 Array of Prefix Codes Interrupt inhibit instruction MOV A FFH NCC MOV ILM imm8 ADD A 01H CCR XXX10XXB CCR XXX10XXB CCR remains unchanged by NCC Prefix code enables PCB Prefix code ADB DTB PCB ADD A 01H ...

Page 75: ...defined by user by executing an instruction such as INT instruction dedicated to the software interrupt Interrupts by extended intelligent I O service EI2OS The extended intelligent I O service EI2 OS provides automatic data transfer between resources and memory Data can be transferred just by creating the startup setting program and end program of the EI2OS At completion of data transfer the inte...

Page 76: ...instruction execution PC updating and pointer transfering to next instruction Dedicated register returns from system stack and returns to the execution befor calling interrupt process Reading interrupt vector updating PC and PCB and branch to the interrupt processing NO NO YES YES NO NO YES YES NO NO Interrupt start return processing During executing instruction of string type they are determinate...

Page 77: ...pt vector Table 3 5 1 List of Interrupt Vectors Software Interrupt Instruction Vector address L Vector Address M Vector address H Mode Data Interrupt number Hardware Interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Unused 0 None INT7 FFFFE0H FFFFE1H FFFFE2H Unused 7 None INT8 FFFFDCH FFFFDDH FFFFDEH FFFFDFH 8 RESET vector INT9 FFFFD8H FFFFD9H FFFFDAH Unused 9 None INT10 FFFFD4H FFFFD5H FFFFD6H Unused 10 Exc...

Page 78: ...H 1 8 10 bit A D converter 18 12H FFFFB4H 16 bit free run timer overflow 19 13H FFFFB0H ICR04 0000B4H Reserved 20 14H FFFFACH Reserved 21 15H FFFFA8H ICR05 0000B5H PPG timer channel 0 1 underflow 22 16H FFFFA4H Input capture 0 fetched 23 17H FFFFA0H ICR06 0000B6H 1 External interrupt INT4 INT5 24 18H FFFF9CH Input capture 1 fetched 25 19H FFFF98H ICR07 0000B7H 2 PPG timer channel 2 3 underflow 26 ...

Page 79: ...en two resources share an ICR register and one specifies the EI2OS the remaining resource cannot use the interrupt 2 Only input capture unit 1 supports EI2OS As the PPG timer does not support EI2OS the PPG timer should be disabled for interrupts when input capture unit 1 uses EI2OS 3 Only CAN wake up supports EI2OS As the timebase timer does not support EI2OS the timebase timer should be disabled ...

Page 80: ...up Timebase timer 0000B3H Interrupt control register 03 ICR03 16 bit reload timer 0 A D converter 0000B4H Interrupt control register 04 ICR04 16 bit free run timer overflow 0000B5H Interrupt control register 05 ICR05 PPG0 1 0000B6H Interrupt control register 06 ICR06 Input capture 0 External interrupt INT4 INT5 0000B7H Interrupt control register 07 ICR07 Input capture 1 PPG2 3 0000B8H Interrupt co...

Page 81: ...rent at write and read Setting of interrupt level of corresponding peripheral Selection of whether to perform normal interrupt or EI2OS for corresponding peripheral Selection of channel of EI2OS Display of end state of EI2OS Note Do not access the interrupt control register ICR using the read modify write instruction because it causes a malfunction ...

Page 82: ...t level setting bit Interrupt level 7 without interruption 4 5 3 2 1 7 bit2 bit1 bit0 R W R W R W R W ICS3 ICS2 ICS1 ICS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Descriptor address bit7 bit6 bit5 bit4 W W W W 6 0 ISE El2 OS chanel select bit El2 OS enable bit When an interrupt occurs start normal interrupt process When an interrupt occurs start El2 OS Chanel bit3 0 1 0 0 0 0 0 0 0 0 1 1 1 ...

Page 83: ...ting bit Interrupt level 7 without interruption 4 5 3 2 1 7 bit2 bit1 bit0 R W R W R W R W R R S1 S0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bit5 bit4 6 0 ISE El2 OS enable bit El2 OS status bit When an interrupt occurs start normal interrupt process When an interrupt occurs start El2 OS bit3 0 1 0 0 1 1 0 1 0 1 When EI2OS in operation or not started Stop state by end of counting Reserved ...

Page 84: ...r ICR Reference The setting of the channel select bits ICR ICS3 to ICS0 is enabled only when starting the EI2OS When starting the EI2OS set the EI2OS enable bit ICR ISE to 1 When not starting the EI2OS set the bit to 0 The channel select bits ICR ICS3 to ICS0 are enabled only at write and the EI2 OS status bits ICR S1 S0 are enabled only at read Configuration of interrupt control register ICR at w...

Page 85: ...ng resources have no EI2OS function this bit must be set to 0 by the program At reset the ISE bit is set to 0 EI2OS channel select bits ICS3 to ICS0 These bits select EI2OS channels The EI2OS descriptor addresses are set according to the setting values of the ICS3 to ICS0 bits At reset the ICS3 to ICS0 are set to 0000B Table 3 5 5 shows the correspondence between the EI2OS channel select bits and ...

Page 86: ...1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H Table 3 5 5 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses 2 2 ICS3 ICS2 ICS1 ICS0 Channel to be Selected Descriptor Address Table 3 5 6 Relationships Between EI2 OS Status Bits and EI2 OS St...

Page 87: ...accepted registers in the CPU are automatically saved in the system stack The interrupt level of the accepted interrupt is stored in the interrupt level mask register ILM then branches to the corresponding interrupt vector Multiple interrupts Multiple hardware interrupts can be started EI2OS When the EI2OS function ends normal interrupt processing is performed Two or more instances of EI2OS are no...

Page 88: ...gister Figure 3 5 5 Hardware Interrupt Request During Write to the Resource Control Register Table 3 5 7 Mechanism Related to Hardware Interrupt Mechanism Related to Hardware Interrupt Function Peripheral Interrupt enable bit interrupt request bit Controls interrupt request from peripheral Interrupt controller Interrupt control register ICR Sets interrupt level and controls EI2OS CPU Interrupt ena...

Page 89: ...ution of the hardware interrupt inhibit instruction and other instructions Hardware interrupt inhibition during execution of software interrupt When a software interrupt is started the interrupt enable flag CCR I is cleared to 0 and the interrupt is disabled Table 3 5 8 Hardware Interrupt Inhibit Instructions Prefix Code Interrupt Inhibit Instruction Instruction that does not accept interrupt requ...

Page 90: ...st acceptance and interrupt processing The CPU compares the received interrupt level ICR IL2 to IL0 with the value of the interrupt level mask register ILM and generates an interrupt processing microcode after end of the current instruction execution if the interrupt level IL is smaller than the value of the interrupt level mask register ILM and an interrupt is enabled CCR I 1 When the EI2 OS enab...

Page 91: ...uest is preferred to the interrupt mask register ILM the interrupt enable flag CCR I is checked 6 When an interrupt is enabled by the interrupt enable flag CCR I 1 the requested interrupt level IL is set to the interrupt level mask register ILM after completion of the current instruction execution 7 The values of the dedicated registers are saved and processing transfers to interrupt processing 8 ...

Page 92: ...ted from the resource generates a hardware interrupt request 7 The interrupt controller saves data in the dedicated registers and processing transits to interrupt processing 8 Execute the program for interrupt generation at interrupt processing 9 Clear the interrupt request from the peripheral 10 Execute the interrupt return instruction RETI to return to the program executed before transition to i...

Page 93: ...en the higher level interrupt processing is terminated the suspended interrupt processing is resumed The interrupt level IL can be set to 0 to 7 The interrupt request set to level 7 is never accepted If an interrupt request with a priority equal to or lower than the interrupt level of the current executing interrupt is generated during interrupt processing unless the setting of the interrupt enabl...

Page 94: ...L2 to IL0 of the A D converter When an interrupt request with an interrupt level of 1 or 0 is generated under this condition processing the generated interrupt is preferred When the interrupt return instruction RETI is executed after the completion of interrupt processing the values of the dedicated registers A DPR ADB DTB PCB PC PS saved in the system stack are returned to each register and the i...

Page 95: ...nterrupt is masked When enabling a hardware interrupt during software interrupt processing set the interrupt enable flag CCR I to 1 during software interrupt processing Operation of software interrupt When the INT instruction is executed the software interrupt processing microcode in the CPU is started The software interrupt processing microcode saves the values of the dedicated registers in the s...

Page 96: ...f unnecessary data Whether to update the buffer address pointer can be specified Whether to update the I O address pointer can be specified Interrupt by EI2 OS termination At completion of data transfer by the EI2OS the end condition is set in the EI2OS status bits ICR S1 S0 and then the processing automatically transits to interrupt processing The EI2 OS termination factor can be determined by ch...

Page 97: ...s are read from the EI2 OS descriptor 4 Data is transferred according to the transfer source and transfer destination address pointers 5 An interrupt factor is cleared automatically CPU 00 Bank area ISD Buffer I O area Interrupt control register ICR Interrupt controller Interrupt request By IOA By BAP Count by DCT By ICS Memory space 3 3 4 2 1 5 ISD EI2 OS Descriptor IOA I O address pointer BAP Bu...

Page 98: ...ISD address Figure 3 5 10 Configuration of EI2 OS Descriptor ISD Data counter upper 8bit DCTH Data counter lower 8bit DCTL I O address pointer upper 8bit IOAH EI2OS status register ISCS I O address pointer lower 8bit IOAL Buffer address pointer upper 8bit BAPH Buffer address pointer middle 8bit BAPM Buffer address pointer lower 8bit BAPL ISD head address 000100H 8 ICS ICS EI2OS channel select bit ...

Page 99: ...81 CHAPTER 3 CPU 8 000140H 9 000148H 10 000150H 11 000158H 12 000160H 13 000168H 14 000170H 15 000178H Table 3 5 9 EI2OS Descriptor ISD Area 2 2 Channel ICR ICS3 to ICS0 Descriptor header Address ...

Page 100: ... address pointer IOA The I O address pointer IOA is a 16 bit register that sets the low addresses A15 to A0 of the 00 bank area where data is transferred to or from the buffer The high addresses A23 to A16 are set all to 0 and the area between 000000H and 00FFFFH can be addressed Figure 3 5 12 shows the configuration of I O address pointer IOA Figure 3 5 12 Configuration of I O Address Pointer IOA...

Page 101: ... W R W R W R W R W R W SE El2 OS terminate control bit Not termination by the termination request from a peripheral resource Termination by the termination request from a peripheral resource bit0 0 1 DIR Data transfer direction specification bit I O address pointer buffer address pointer Buffer address pointer I O address pointer bit1 0 1 BF BAP updating fixed select bit Buffer address pointer is ...

Page 102: ... BAPH BAPL and does not change in the higher 8 bits BAPH Figure 3 5 14 shows the configuration of the buffer address pointer BAP Figure 3 5 14 Configuration of Buffer Address Pointer BAP Reference The area that can be set by the I O address pointer IOA is 000000H to 00FFFFH The area that can be set by the buffer address pointer BAP is 000000H to FFFFFFH The maximum transfer count that can be set b...

Page 103: ...heral resource ISE 1 ISD ISCS rread Clear of peripheral resourceinterruptewquest CPU operation return DCT decrement Set 00B to S1 S0 DIR 1 IF 0 BF 0 DCT 00H Address setting for BAP Data transfer Address setting for IOA Interrupt processing Clear ISE to 0 Interrupt processing BAP updating IOA updating Set 11B to S1 S0 Set 01B to S1 S0 SE 1 ISD ISCS IF BW BF DIR SE DCT IOA BAP ISE S1 S0 EI2OS descri...

Page 104: ...ration of resource and interrupt enable bit Setting ILM I in PS Execution of user program Resetting of intelligent I O Service Switching channels Data processing during buffer RETI Data transfer Transfer termination of specified number or Identification of transfer to interrupt by termination request from peripheral resources NO YES Interrupt request and ISE 1 transfer to interrupt processing ISE ...

Page 105: ...tions at executing EI2OS as shown in Table 3 5 11 Table 3 5 10 Extended Intelligent I O Service Execution Time Setting of the EI2OS termination control bit SE Termination by the termination request from a peripheral resource The termination request from the peripheral resource is ignored Setting of the IOA updating fixing select bit IF fixed Update fixed Update Setting of BAP address updating fixi...

Page 106: ...s processing by the termination request from a resource ICR S1 S0 11B processing transits to interrupt processing The EI2OS processing time at a termination request from a resource is calculated as follows Interrupt handling time El2OS Processing Time at continuing data transfer 21 6 Z Machine clock Z compensation value of interrupt handling time El2OS Processing Time after count finish Table 3 5 ...

Page 107: ...following processing is performed before the transition to interrupt processing The values of dedicated registers A DPR ADB DTB PCB PC PS are saved to the system stack The interrupt enable flag CCR I cleared to 0 and interrupts disabled The stack flag CCR S set to 1 The value of the program counter PC saved in the stack is a value of the address where undefined instructions are stored For instruct...

Page 108: ...quest during execution of each instruction as a result wait time occurs Interrupt handling time θ machine cycles The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the system stack and fetch the interrupt vector table address after accepting the interrupt request The interrupt handling time θ is obtained using the following equations θ 24 6 x Z machi...

Page 109: ...nsation Value Z of Interrupt Handling Time Address Set by Stack Pointer Compensation Value Z For internal area even address 0 For internal area odd address 2 Reference One machine cycle is equal to one clock cycle of the machine clock φ ...

Page 110: ...the stack operation at starting interrupt processing Figure 3 5 18 Stack Operation at Starting Interrupt Processing Stack Operation at Return from Interrupt Processing When the interrupt return instruction RETI is executed after completion of interrupt processing the values of the dedicated registers PS PC PCB DTB ADB DPR AL AH are returned to each register from the system stack and the dedicated ...

Page 111: ...ntrol register STACK SSEG Stack RW 100 STACK_T RW 1 STACK ENDS Main program CODE CSEG START MOV RP 0 Using the head bank as general purpose register MOV ILM 07H Setting ILM in PS to level 7 MOV A STACK_T Setting of system stack MOV SSB A MOVW A STACK_T Setting of stack pointer MOVW SP A in this case S flag 1 so set to SSP MOV DDR2 00000000B Setting P24 INT4 pin to input OR CCR 40H I flag of CCR in...

Page 112: ...FD0H Setting vector to interrupt 11 0BH DSL ED_INT1 ORG 0FFDCH Setteing of reset vector DSL START DB 00H Setting to single chip mode VECT ENDS END START DDR2 EQU 000012H Port 2 direction register ENIR EQU 000030H Interrupt DTP enable register EIRR EQU 000031H Interrupt DTP factor register ELVR EQU 000032H Request level setting register ICR00 EQU 0000B0H Interrupt control register BAPL EQU 000100H ...

Page 113: ...dress port 2 000002H MOV IOAH 00H MOV DCTL 64H Setting transmission byte number 100 bytes MOV DCTH 00H MOV I ICR00 00001000B EI2OS channel 0 EI2OS enable Interrupt level 0 strongest MOV I ELVR 00010000B Regard INT4 as H level request MOV I EIRR 00H Clear interrupt factor of INT4 MOV I ENIR 10H Interrupt enable of INT4 MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H I flag of CCR in PS set to i...

Page 114: ...scillation stabilization wait time is not generated by a watchdog timer reset Software reset The software reset occurs when 0 is written to the internal reset signal generation bit LPMCR RST in the low power consumption mode control register The oscillation stabilization wait time is not generated by a software reset External reset The external reset occurs when a Low level is input to the externa...

Page 115: ...ally For a string instruction such as MOVS the reset cancel wait state may be set before completion of transfer by a specified counter value To return from stop mode subclock mode subsleep mode or watch mode to main clock mode using the external reset pin RST pin input the Low level for at least oscillator s oscillation time 100 µs 16 machine cycles main clock The oscillation time for the oscillat...

Page 116: ...ower on reset Table 3 6 2 Reset Factors and Oscillation Stabilization Wait Times Reset Factor Oscillation Stabilization Wait Time Parenthesized values are examples calculated at an oscillation clock frequency of 4 MHz Power on reset 216 HCLK watchdog reset None Software reset None External reset None HCLK Oscillation clock frequency MB90V495G requires 218 HCLK VCC CLK CPU operation 215 HCLK Oscill...

Page 117: ...HCLK Oscillation clock frequency 1 MB90V495G requires 215 HCLK when WS1 0 10 and 217 HCLK when WS1 0 11 2 The oscillation stabilization wait time taken when the power supply is turned on is fixed at 216 HCLK about 16 38 ms However MB90V495G is fixed at 218 HCLK approximately 65 54ms Note Ceramic or crystal oscillators require an oscillation stabilization wait time of several milliseconds to some t...

Page 118: ...Notes To prevent memory from being broken due to a reset during writing to memory a Low level is input to the RST pin in a machine cycle in which memory is not broken The CPU operation clock is required to initialize internal circuits During operation using an external clock in particular the reset signal and CPU operation clock signal must be input Pin RST Pch Nch Input buffer Internal reset siga...

Page 119: ...n which the oscillation clock is stopped and oscillation stabilization wait time of 2 15 HCLK approximately 8 19 ms when the oscillation clock operates at 4 MHz is generated MB90V495G requires an oscillation stabilization wait time of 217 HCLK about 32 77 ms Mode Pin The MD0 to MD2 mode pins are external pins They are used to set the mode for reading data and reset vectors Power on reset Software ...

Page 120: ...de or a memory access area It is allocated to address FFFFDFH During the reset operation this data is read automatically by a mode fetch and stored in the mode register Reset vectors The reset vectors are the start addresses of execution after completion of the reset operation They are allocated to addresses FFFFDCH to FFFFDEH During the reset operation these vectors are read automatically by a mo...

Page 121: ...peration read the value of the watchdog timer control register WDTC by software to branch to the appropriate program Figure 3 6 5 Block Diagram of Reset Factor Bits Power on generate detection circuit External reset request detection circuit Watchdog taimer reset generate detection circuit LPMCR register RST bit program detection circuit RST L Power on Delay circuit S R F F Q S R F F Q S R F F Q S...

Page 122: ... R W W W R R R SRST WT1 WTE ERST WRST bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reset value XXXXX111B Watchdog timer control register WDTC Write only W Indefined X Read only R WT0 PONR Table 3 6 4 Correspondence of Reset Factor Bit and Reset Factor Reset Factor PONR WRST ERST SRST Generating power on reset 1 X X X Reset by watchdog timer 1 Input of external reset signal to RST pin 1 Software reset b...

Page 123: ...according to each reset factor even when two or more reset factors are generated For example if the watchdog timer overflows and an external reset request is generated from the RST pin at the same time both WRST and ERST bits are set to 1 after completion of the reset operation Clearing of reset factor bit Once set the reset factor bit is not cleared even if any reset factor other than the set fac...

Page 124: ... internal vector mode set If the internal vector mode is set all I O pins enter the high impedance state and mode data is read to internal ROM State of Pins after Mode Data Read The I O pins are all set to the high impedance state and the mode data read destination is the internal ROM Note Be careful not to let those devices malfunction which are connected to pins that enter the high impedance sta...

Page 125: ... The PLL clock multiplying circuit can be used to generate four clocks for multiplying the oscillation clock The clock generation section controls the oscillation stabilization wait time PLL clock multiplying circuit and selects internal clock by the clock selector Oscillation clock HCLK This clock is generated by connecting an oscillator or inputting an external clock to the high speed oscillatio...

Page 126: ...lation clock can oscillate at 3 to 16 MHz The maximum operating frequency of the CPU and peripheral resources is 16 MHz If a multiplier that exceeds the maximum operating frequency is set the device does not operate normally When the oscillation clock frequency is 16 MHz therefore the PLL clock multiplier can be set only to 1 The PLL oscillator oscillates in the range of 3 to 16 MHz which varies d...

Page 127: ...ap Time base timer PLL multiplying circuit Clock selector 8 16 bit PPG timer 0 1 8 16 bit PPG timer 2 3 16 bit reload timer 0 Communication prescaler 1 Input capture unit Oscillation stabilization waiting time Watchdog timer Oscillation clock generator Pin Pin 1 2 3 4 X1 X0 X1A X0A HCLK MCLK SCLK PCLK Pin TIN0 Clock generator Peripheral functions HCLK Oscillation clock PCLK PLL clock SCLK Sub cloc...

Page 128: ...ock control circuit CPUintermittent operation cycle selector S Q R S Q R S Q R Reset Interrupt CPU operation clock Peripheral function operation clock Standby control cicuit Oscillation clock generator HCLK Sub clock Operation clock selector Oscillation stabilization wait time selector Oscillation clock Machine clock X0 X1 Pin Pin Clock select register CKSCR Low power Consumption mode control regi...

Page 129: ...it as a PLL clock PCLK to the clock selector Clock selector This selector selects the clock that is supplied to the CPU or resources from the main clock sub clock and four types of PLL clock Clock select register CKSCR This register is used to select between the oscillation clock and PLL clock between the main clock and subclock the oscillation stabilization wait time and the PLL clock multiplier ...

Page 130: ...n This section explains the register in the clock generation section Register in Clock Generation Section and List of Reset Values Figure 3 7 3 Clock Select Register and List of Reset Values 1 0 1 Clock select register CKSCR 1 1 1 14 13 12 11 10 9 0 1 15 8 bit ...

Page 131: ...bit bit10 SCS 0 1 Select sub clock Select main clock Sub clock select bit bit11 R W R W R W R W R W R W R R 1 HCLK 4MHz 2 HCLK 8MHz 3 HCLK 12MHz 4 HCLK 16MHz PSCCR bit9 bit8 CS2 CS1 Multiplying select bit Parenthesized values are examples calculated at an oscillation clock frequency of 4 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 210 HCLK approx 256 µs 213 HCLK approx 2 05ms 214 HCLK approx 4 1ms 215 HCL...

Page 132: ...t thereby setting the subclock mode 2 When switching from the main clock to PLL clock CKSCR MCS 1 0 use the timebase timer interrupt enable bit TBTC TBIE or interrupt level mask register ILM ILM2 to 0 to disable timebase timer interrupts before writing 0 to the PLL clock select bit bit11 SCS sub clock selection bit This bit indicates the main clock or sub clock to be selected as the machine clock ...

Page 133: ... to PLL clock mode the oscillation stabilization wait time follows the values specified in these bits The PLL clock requires an oscillation stabilization wait time of at least 214 HCLK For switching from subclock mode to PLL clock mode therefore set these bits to 10B or 11B bit14 MCM PLL clock operation flag bit The bit indicates the main clock or PLL clock currently selected as the machine clock ...

Page 134: ... or 4 depending on the combination of the clock select register CKSCR CS0 CS1 and this register PSCCR CS2 This register must always be set in main clock mode Table 3 7 2 Functions of PLL subclock control register PSCCR Reserved Reserved SCDS 14 13 12 11 10 9 CS2 15 8 bit W W W W Read Write Address 003FH X X X 0 0 0 X 0 Initial value bit name Function bit15 to bit12 Unused bits Write No effect on o...

Page 135: ...uming a frequency of 4 MHz CS2 CS1 CS0 Function 0 0 0 1 HCLK 4 MHz 0 0 1 2 HCLK 8 MHz 0 1 0 3 HCLK 12 MHz 0 1 1 4 HCLK 16 MHz 1 0 0 2 HCLK 8 MHz 1 0 1 4 HCLK 16 MHz 1 1 0 Unavailable 1 1 1 Unavailable Note This feature is not provided for the MB90V495G This register therefore returns 1 whenever read ...

Page 136: ...rals The PLL clock multiplication rate can be set using the clock select register CKSCR CS1 CS0 Transition of Clock Mode In clock modes the setting of the PLL clock select bit CKSCR MCS and sub clock select bit CKSCR SCS transits to the main clock mode sub clock mode or PLL clock mode Transition from main clock mode to PLL clock mode If the PLL clock select bit CKSCR MCS is rewritten from 1 to 0 t...

Page 137: ...for at least oscillator s oscillation time 100 µs 16 machine cycles main clock The oscillation time for the oscillator is the period of time taken until its amplitude reaches 90 It takes several to dozens of ms for crystal oscillators hundreds of µs to several ms for FAR ceramic oscillators and 0 ms for external clocks There is no sub clock in MB90F897S Notes The machine clock is not switched imme...

Page 138: ... 01 PLL3 mutiplier MCS 0 MCM 0 SCS 1 SCM 1 CS1 CS0 10 PLL4 mutiplier MCS 0 MCM 0 SCS 1 SCM 1 CS1 CS0 11 Main PLLx MCS 0 MCM 1 SCS 1 SCM 1 CS1 CS0 xx PLL1 Main MCS 1 MCM 0 SCS 1 SCM 1 CS1 CS0 00 PLL2 Main MCS 1 MCM 0 SCS 1 SCM 1 CS1 CS0 01 PLL3 Main MCS 1 MCM 0 SCS 1 SCM 1 CS1 CS0 10 PLL4 Main MCS 1 MCM 0 SCS 1 SCM 1 CS1 CS0 11 Sub PLL MCS 0 MCM 1 SCS 1 SCM 0 CS1 CS0 xx PLL1 Sub MCS 1 MCM 0 SCS 0 S...

Page 139: ...ation stabilization wait time CS1 CS0 01 14 Termination of main clock oscillation stabilization wait time CS1 CS0 10 15 Termination of main clock oscillation stabilization wait time CS1 CS0 11 16 SCS bit 1 write MCS bit 0 wreit 17 Synchronous timing of PLL clock and ub ckock MCS PLL clock selector bit of Clock selecter register CKSCR MCM PLL clock indicate bit of Clock selecter register CKSCR SCS ...

Page 140: ...wait time the machine clock is supplied to the CPU The oscillation stabilization wait time varies with the type of oscillator ceramic crystal etc It is necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used The oscillation stabilization wait time can be selected using the clock select register CKSCR When the clock mode changes from main clock mode to PLL ...

Page 141: ...ion pins can be used as oscillation clocks Connection of Oscillator and External Clock Example of connection of crystal oscillator or ceramic oscillator Figure 3 7 8 Example of connection of crystal oscillator or ceramic oscillator Example of connection of external clock Figure 3 7 9 Example of connection of external clock Note There is no sub clock in MB90F897S MB90895 series X0 X1 C1 C2 X0A X1A ...

Page 142: ... 1 shows the relationships between the CPU operation mode and current consumption Figure 3 8 1 CPU Operation Modes and Current Consumption CPU CPU operating mode Consumption current PLL clock mode 4 multiplier clock 3 multiplier clock 2 multiplier clock 1 multiplier clock PLL clockintermittent operating mode Main clock mode 21 HCLK Main clock intermittent operating mode Standby mode 4 multiplier c...

Page 143: ... operation with the high speed clock supplied to the peripherals to reduce the power consumption In this mode the intermittent clock is input to only the CPU at accessing registers internal memory resources or at the external access Standby Mode The standby mode causes the standby control circuit to stop the supply of an operation clock to the CPU or peripherals or to stop the oscillation clock HC...

Page 144: ...a to be retained with the least power consumption Notes While the clock mode is being switched do not switch the CPU to any other clock mode or to low power consumption mode until the current process of mode switching is completed Check the MCM and SCM bits in the clock select register CKSCR to make sure that the transition to the new clock mode has been completed If the mode is switched to anothe...

Page 145: ...ck generator Sub clock generator Sub clock SCLK Clock generator Operating clock selector Machine clock Oscillation stabilization selector Oscillation clock HCLK X0 2 X1 Clock select register CKSCR Low power consumption mode control register LPMCR Clock sleep and stop signal Clock and stop signal Select the intermittent cycle Internal reset generator Pin High Z control circuit Internal reset Pin Hi...

Page 146: ... standby mode CPU clock controller This controller supplies an operating clock to the CPU Pin high impedance controller This controller causes the input output pins to become high impedance in the watch mode timebase timer mode and stop mode Internal reset generator This generator generates the internal reset signal Low power consumption mode control register LPMCR This register transits a clock m...

Page 147: ... explains the registers to be used to set lower power consumption modes Low power Consumption Mode Control Register and Reset Values Figure 3 8 3 Low power Consumption Mode Control Register and Reset Values 1 0 0 Low power consumption control register LPMCR 1 0 0 6 5 4 3 2 1 0 0 7 0 bit ...

Page 148: ...ead Write R W Write only W TMD 0 1 Transfer to clock mode or timebase timer mode No effect 0 cycle CPU clock peripheral clock 8 cycle CPU clock peripheral clock 1 approx 3 to 4 16 cycle CPU clock peripheral clock 1 approx 5 to 6 32 cycle CPU clock peripheral clock 1 approx 9 to 10 Clock mode bit bit3 RST 0 1 Generate the internal reset of 3 machine cycle No effect Internal reset signal generation ...

Page 149: ...initialized to 0 at a reset bit6 SLP sleep mode bit Shift to sleep mode When the bit is set to 0 No effect When the bit is set to 1 The CPU enters the sleep mode The bit is initialized to 0 when a reset or external interrupt occurs When the STP and SLP bits are set to 1 at the same time the STP bit supersedes the SLP bit causing a transition to stop mode bit7 STP stop mode bit Transiting to the st...

Page 150: ...ource or as a port in stop mode watch mode or timebase timer mode disable the output of the peripheral resource then set the STP bit of the low power consumption mode control register LPMCR to 1 or set the TMD bit to 0 This applies to the following pins P21 TOT0 P23 TOT1 There is no sub clock in MB90F897S Table 3 8 2 Instructions at Transition to Low power Consumption Mode MOV io imm8 MOV dir imm8...

Page 151: ... supplying a high speed clock to resources reduces the power consumption The count of machine cycles in which clock supply to the CPU halts is set by the CG1 and CG0 bits in the low power consumption mode control register LPMCR The instruction execution time in the CPU intermittent operation mode is determined by adding the normal execution time to the compensation value obtained by multiplying co...

Page 152: ...LK Sub clock SCLK Machine clock CPU Resource pin Setting disabled Sleep mode Main sleep mode MCS 1 SCS 1 SLP 1 external reset or interrupt Sub sleep mode MCS X SCS 0 SLP 1 external reset or interrupt PLL sleep mode MCS 0 SCS 1 SLP 1 external reset or interrupt timebase timer mode SPL 0 MCS X SCS 1 TMD 0 1 external reset or interrupt 4 SPL 1 MCS X SCS 1 TMD 0 1 Hi Z 3 external reset or interrupt 4 ...

Page 153: ...interrupts 6 External interrupt INT6 INT7 MCS PLL clock select bit in clock select register CKSCR SCS subclock select bit in the clock select register CKSCR SPL setting pin state bit of low power consumption mode control register LPMCR SLP sleep mode bit of low power consumption mode control register LPMCR STP stop mode bit of low power consumption mode control register LPMCR TMD clock mode bit of...

Page 154: ...to 1 the mode does not transit to the sleep mode If the CPU is not ready to accept any interrupt request the instruction next to the currently executing instruction is executed If the CPU is ready to accept any interrupt request an interrupt operation immediately branches to the interrupt processing routine Pin state In the sleep mode pins other than those used for bus input output or bus control ...

Page 155: ...en the CPU is ready to accept any interrupt request it branches immediately to the interrupt processing routine Figure 3 8 6 shows the cancellation of sleep mode by an interrupt Figure 3 8 6 Cancellation of Sleep Mode by Interrupt Notes For returning from subsleep mode to main clock mode using the external reset pin RST pin input the Low level for at least oscillator s oscillation time 100 µs 16 m...

Page 156: ...it to the watch mode If the CPU is not ready to accept any interrupt request the instruction next to the currently executing instruction is executed If the CPU is ready to accept any interrupt request an interrupt operation immediately branches to the interrupt processing routine Pin state In the watch mode the input output pins can be set to the high impedance state or held in the state before tr...

Page 157: ...ation wait time is generated and the interrupt request is identified immediately after return from the watch mode When the CPU is not ready to accept any interrupt request the next instruction to the currently executing instruction is executed When the CPU is ready to accept any interrupt request it branches immediately to the interrupt processing routine Notes To return from watch mode to main cl...

Page 158: ...trol register LPMCR set to 0 the mode does not transit to the timebase timer mode If the CPU is not ready to accept any interrupt request the instruction next to the currently executing instruction is executed If the CPU is ready to accept any interrupt request an interrupt operation immediately branches to the interrupt processing routine Pin state In the timebase timer mode the input output pins...

Page 159: ...e condition code register CCR the interrupt level mask register ILM and the interrupt control register ICR When the CPU is not ready to accept any interrupt request the nest instruction to the currently executing instruction is executed When the CPU is ready to accept any interrupt request it branches immediately to the interrupt processing routine The following two timebase timer modes are availa...

Page 160: ... power consumption mode control register LPMCR set to 1 the mode does not transit to the stop mode If the CPU is not ready to accept any interrupt request the next instruction to the currently executing instruction is executed If the CPU is ready to accept any interrupt request an interrupt operation immediately branches to the interrupt processing routine Pin state In the stop mode the input outp...

Page 161: ... resource or as a port in stop mode disable the output of the peripheral resource then set the STP bit of to 1 Listed below are applicable ports This applies to the following pins P14 PPG0 P15 PPG1 P16 PPG2 P17 PPG3 P21 TOT0 P23 TOT1 Notes To return from stop mode to main clock mode using the external reset pin RST pin input the Low level for at least oscillator s oscillation time 100 µs 16 machin...

Page 162: ...errupt processing routine Note When handling an interrupt the CPU usually services the interrupt after executing the instruction that follows the one specifying the stop mode In PLL stop mode the main clock and PLL multiplier circuit remain stopped When the CPU returns from PLL stop mode therefore it is necessary to allow for the main clock oscillation stabilization wait time and PLL clock oscilla...

Page 163: ...ock oscillation stabilization wait PLL sleep mode PLL stop mode Main clock oscillation stabilization wait Main sleep mode Timebase timer mode Timebase timer mode Main stop mode Main clock oscillation stabilization wait Interrupt Interrupt SLP 1 Interrupt SLP 1 Interrupt TMD 0 Interrupt TMD 0 Interrupt TMD 0 STP 1 STP 1 STP 1 Interrupt SCS 0 SCS 1 Notes While the clock mode is being switched do not...

Page 164: ...it is means that when the resource with an output is in operation the state of pins is output according to the state of the resource and when the state of output pins is output it is held Input disabled means that no pin value can be accepted internally because the internal circuit is off while the operation of the input gates of pins is enabled 2 Input cut off means that the operation of the inpu...

Page 165: ...not Notes on the Transition to Standby Mode To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode watch mode or timebase timer mode use the following procedure 1 Disable the output of peripheral functions 2 Set the SPL bit to 1 STP bit to 1 or TMD bit to 0 in the low power mode control register LPMCR Note on Canceling Standby Mode The standby mode c...

Page 166: ...scillation stabilization wait time whichever is longer The PLL clock requires an oscillation stabilization wait time of at least 214 HCLK For switching to PLL clock mode therefore set the CKSCR WS1 and WS0 bits to 10B or 11B In PLL stop mode the main clock and PLL multiplier circuit remain stopped When the CPU returns from PLL stop mode therefore it is necessary to allow for the main clock oscilla...

Page 167: ... use one of the following methods 1 to 3 to access the register 1 Specify the standby mode transition instruction as a function and insert two __wait_nop built in functions after that instruction If any interrupt other than the interrupt to return from the standby mode can occur within the function optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring...

Page 168: ...instruction between pragma asm and pragma endasm and insert two NOP and JMP instructions after that instruction Example Transition to stop mode progrma asm MOVI _IO_LPMCR H 58 Set LPMCR SLP bit to 1 NOP NOP JMP 3 Jump to the next instruction progrma endasm ...

Page 169: ...y the mode pins MD2 to MD0 RUN modes The RUN mode is the normal CPU operation mode It provides various low power consumption modes such as the main clock mode PLL clock mode and sub clock mode Flash serial programming mode and flash memory mode Some products in MB90895 series have user programmable flash memory The flash serial programming mode is that for serially programming data to flash memory...

Page 170: ...s are read from internal ROM Flash serial programming mode Flash serial programming cannot be performed just by the settings of the mode pins Flash memory mode This mode is set when using a parallel writer Setting of Mode Pins Set the mode pins as shown in Figure 3 9 1 Table 3 9 2 Setting of Mode Pins Mode Pin Mode Name MD2 MD1 MD0 0 0 0 Setting disabled 0 0 1 0 1 0 0 1 1 Internal vector mode 1 0 ...

Page 171: ...ow of Mode Pin Setting MD2 to MD0 Set to 0 Vss 1 Vcc And also do not set to other than above description Setting the pin mode Flash memory programing NO YES Flash programing mode MD2 1 MD1 1 MD0 1 Internal vector mode MD2 0 MD1 1 MD0 1 ...

Page 172: ...equence Figure 3 9 2 Mode Data 12 13 11 10 9 8 15 R W R W R W R W R W R W R W R W 14 Bus mode setting bit M1 0 0 1 1 Reserved 0 Reserved bit Be sure to set this bit to 0 bit8 bit9 bit10 bit11 bit12 bit13 Single chip mode bit15 bit14 Reset value Undefined X Read Write R W M0 0 1 0 1 Setting prohibited Table 3 9 3 function of mode register bit name Function bit8 to bit13 Reserved reserved bit Be sur...

Page 173: ...CPU Setting Mode Data Set the mode data as shown in Figure 3 9 3 Figure 3 9 3 Flow of Mode Data Setting Do not set mode data other than above value Setting of mode data Single chip mode Single chip mode Mode data 00H ...

Page 174: ...ternal RAM are used and no external access occurs Ports 1 to 3 can be used as general purpose I O ports Reference For details on access areas see 3 1 Memory Space In MB90F897 S if read the FE0000H FEFFFFH area can be read the data of FF0000H FFFFFFH ROM area When ROM mirror is enabled ROM area imge of FF Bank Address 1 FFFFFFH 003900H 004000H 010000H FE0000H 000100H 0000C0H 000000H RAM area Extend...

Page 175: ...referencing the settings of the mode pins and mode data Figure 3 9 5 Operations for Selecting Memory Access Mode Generate the reset factor Internal data read to internal ROM Fetch the mode data and reset vectors from internal ROM Setting the single chip mode Setting of mode pin MD2 1 0 M1 and M0 bit of mode data During reset operation M1 M0 00B All I O pins are High Z YES NO Check the mode pin Che...

Page 176: ...158 CHAPTER 3 CPU ...

Page 177: ...scribes the function and operation of the I O port 4 1 Overview of I O Ports 4 2 Registers of I O Port and Assignment of Pins Serving as External Bus 4 3 Port 1 4 4 Port2 4 5 Port 3 4 6 Port 4 4 7 Port 5 4 8 Port input level select register ...

Page 178: ...put pin Table 4 1 1 List of Each Port Functions Port Name Pin Name Input Type Output Type Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port 1 P10 IN0 to P13 IN3 CMOS hysteresis Automotive CMOS 1 CMOS General purpose I O ports P17 P16 P15 P14 P13 P12 P11 P10 P14 PPG0 to P17 PPG3 CMOS high current Resource PPG3 PPG2 PPG1 PPG0 IN3 IN2 IN1 IN0 port 2 P20 TIN0 to P27 INT7 CMOS General purpose I O p...

Page 179: ... XXXXXXXXB Port 2 data register PDR2 R W 000002H XXXXXXXXB Port 3 data register PDR3 R W 000003H XXXXXXXXB Port 4 data register PDR4 R W 000004H XXXXXXXXB Port 5 data register PDR5 R W 000005H XXXXXXXXB Port 1 direction register DDR1 R W 000011H 00000000B Port 2 direction register DDR2 R W 000012H 00000000B Port 3 direction register DDR3 R W 000013H 000X0000B Port 4 direction register DDR4 R W 000...

Page 180: ...ves as a resource pin it cannot be used as a general purpose I O port when used as a peripheral When using port 1 as the input pin of the peripheral set the pin corresponding to the resource in the DDR1 as an input port When using the port as the output of the resource set the output of the corresponding resource to enabled Port 1 functions as the output pin of the resource regardless of the setti...

Page 181: ... latch Pin Port data register PDR DDR read DDR write Port direction register DDR PDR write PDR read Direction latch Standby control SPL 1 Standby control Control of stop mode SPL 1 timebase timer mode SPL 1 and clock mode SPL 1 Pch Nch Resource output acceptance Resource input Resource output Internal data bus Table 4 3 2 The correspondence between the registers and pins of port 1 Port Name Bits o...

Page 182: ...is set for the output latch and when the pin is an output port pin the Low level is output to the pin R W 000001H XXXXXXXXB 1 The pin state is High level 1 is set for the output latch and when the pin is an output port pin the High level is output to the pin Port 1 direction register DDR1 0 The direction latch is 0 The output buffer is set to OFF and the pin becomes an input port pin R W 000011H 0...

Page 183: ... output is preferred enabled the resource output functions regardless of the settings of the DDR1 When the pin state is read with the resource output set to enabled the output state of the resource is read Operation of resource input The state of the pin that serves as the resource input is input to the resource When using port 1 as the input pin of the resource clear the bit in the DDR1 correspon...

Page 184: ...e Stop Mode Timebase Timer Mode or Watch Mode SPL 0 SPL 1 P10 IN0 to P17 PPG3 General purpose I O ports General purpose I O ports General purpose I O ports Input cut off and output becomes Hi Z Pull up resistor disconnected SPL Pin state specification bit of low power consumption mode control register LPMCR SPL Hi Z High impedance Note To set that pin to high impedance which serves either as a per...

Page 185: ...P27 INT7 Port 2 data register PDR2 Port 2 direction register DDR2 High address control register HACR Pin Assignment of Port 2 The pin is used either a resource pin or a general purpose I O pin Since the port serves as resource pin when used as a resource pin the port cannot be used as general purpose I O port When using port 2 as the input pin of the resource set the pin corresponding to the resou...

Page 186: ...N0 P20 Genera l purpos e I O TIN0 16 bit reload timer 0 input CMOS CMOS hysteresis Automotive CMOS D P21 TOT0 P21 TOT0 16 pit reload timer 0 output P22 TIN1 P22 TIN1 16 bit reload timer 1 input P23 TOT1 P23 TOT1 16 bit reload timer 1 output P24 INT4 P24 INT4 External interrupt input P25 INT5 P25 INT5 P26 INT6 P26 INT6 P27 INT7 P27 INT7 Reference For the circuit type see Section 1 7 I O Circuit ...

Page 187: ...t latch Pin Port data register PDR DDR read DDR write Port direction register DDR PDR write PDR read Direction latch Standby control SPL 1 Standby control Control of stop mode SPL 1 timebase timer mode SPL 1 and clock mode SPL 1 Pch Nch Resource output acceptance Resource input Resource output Internal data bus Table 4 4 2 The correspondence between the registers and pins of port 2 Port Name Bits ...

Page 188: ...state is Low level 0 is set for the output latch and when the pin is an output port pin the Low level is output to the pin R W 000002H XXXXXXXXB 1 The pin state is High level 1 is set for the output latch and when the pin is an output port pin the High level is output to the pin Port 2 direction register DDR2 0 The direction latch is 0 The output buffer is set to OFF and the pin becomes an input p...

Page 189: ... PDR2 but not output to the pin When the PDR2 is read the level value Low or High of the pin is read Operation of resource output When using the port as the output pin of the resource set the resource output to enabled Since the resource output is preferred enabled the resource output functions regardless of the settings of the DDR2 When the pin state is read with the resource output set to enable...

Page 190: ...he pin enters the high impedance state Because the output buffer is set forcibly to OFF irrespective of the value of the DDR2 Table 4 4 4 shows the state of the port 2 pins Table 4 4 4 The state of the port 2 pins Pin Name Normal Operation Sleep mode Stop Mode Timebase Timer Mode or Watch Mode SPL 0 SPL 1 P20 TIN0 to P27 INT7 General purpose I O ports General purpose I O ports General purpose I O ...

Page 191: ...neral purpose I O port when used as a resource When using port 4 as the input pin of the resource set the pin corresponding to the resource in the DDR4 as an input port Table 4 5 1 shows pin assignment of port 3 Table 4 5 1 Pin Assignment of Port 3 Port Name Pin Name Port Function Resource I O Type Circu it Type Input Output port 3 P30 SOT0 P30 General purpose I O SOT0 UART0 serial clock output CM...

Page 192: ...her P35 nor P36 Output latch Pin Port data register PDR DDR read DDR write Port direction register DDR PDR write PDR read Direction latch Standby control SPL 1 Standby control Control of stop mode SPL 1 timebase timer mode SPL 1 and clock mode SPL 1 Pch Nch Resource output acceptance Resource input Resource output Internal data bus Table 4 5 2 Correspondence between Registers and Pins for Port 3 P...

Page 193: ...r the output latch and when the pin is an output port pin the Low level is output to the pin R W 000003H XXXXXXXXB 1 The pin state is High level 1 is set for the output latch and when the pin is an output port pin the High level is output to the pin Port 3 direction register DDR3 0 The direction latch is 0 The output buffer is set to OFF and the pin becomes an input port pin R W 000013H 000X0000B ...

Page 194: ...n of the resource clear the bit in the DDR3 corresponding to the input pin of the resource to 0 and set the input pin as an input port Operation at reset When the CPU is reset the value of the DDR3 is cleared to 0 Consequently all output buffers are set to OFF the pin becomes an input port pin and the pin enters the high impedance state The PDR3 is not initialized by reset Therefore when using por...

Page 195: ...eration Sleep mode Stop Mode Timebase Timer Mode or Watch Mode SPL 0 SPL 1 P30 to P33 P35 X0A to P37 ADTG General purpose I O ports General purpose I O ports General purpose I O ports Input cut off and output becomes Hi Z SPL Pin state specification bit of low power consumption mode control register LPMCR SPL Hi Z High impedance ...

Page 196: ...en used as a resource When using port 4 as the input pin of the resource set the pin corresponding to the resource in the DDR4 as an input port When using the port as the output of the resource set the output of the corresponding resource to enabled Port 4 functions as the output pin of the resource regardless of the settings of the DDR4 Table 4 6 1 shows pin assignment of port 4 Table 4 6 1 Pin A...

Page 197: ...Pch Nch Internal data bus Output latch Port data register PDR PDR write PDR read Resource input Resource output Resource output acceptance DDR read DDR write Port direction register DDR Direction latch Standby control SPL 1 Standby control Control of stop mode SPL 1 timebase timer mode SPL 1 and clock mode SPL 1 Table 4 6 2 Correspondence between Registers and Pins for Port 4 Port Name Bits of Rel...

Page 198: ...s Low level 0 is set for the output latch and when the pin is an output port pin the Low level is output to the pin R W 000004H XXXXXXXXB 1 The pin state is High level 1 is set for the output latch and when the pin is an output port pin the High level is output to the pin Port 4 direction register DDR4 0 The direction latch is 0 The output buffer is set to OFF and the pin becomes an input port pin...

Page 199: ...nce the resource output is preferred enabled the resource output functions regardless of the settings of the DDR4 When the pin state is read with the resource output set to enabled the output state of the resource is read Operation of resource input The state of the pin that serves as the resource input is input to the resource When using port 4 as the input pin of the resource clear the bit in th...

Page 200: ...er is forcibly set to off regardless of the values of the Port 4 direction register DDR4 Table 4 6 4 shows the state of the port 4 pins Table 4 6 4 The state of the port 4 pins Pin Name Normal Operation Sleep mode Stop Mode Timebase Timer Mode or Watch Mode SPL 0 SPL 1 P40 SIN1 to P44 RX General purpose I O ports General purpose I O ports General purpose I O ports Input cut off and output becomes ...

Page 201: ...eneral purpose I O port analog input pins P50 AN0 to P57AN7 Port 5 data register PDR5 Port 5 direction register DDR5 Analog input enable register ADER Pins Assignment of Port 5 The pin is used either as an analog input pin or a general purpose I O pin Since port 5 serves as an analog input pin it cannot be used as a general purpose I O port when used as an analog input pin When using port 5 as an ...

Page 202: ...pose I O AN0 Analog input channel 0 CMOS hysteresis analog input Automotive CMOS E P51 AN1 P51 AN1 Analog input channel 1 P52 AN2 P52 AN2 Analog input channel 2 P53 AN3 P53 AN3 Analog input channel 3 P54 AN4 P54 AN4 Analog input channel 4 P55 AN5 P55 AN5 Analog input channel 5 P56 AN6 P56 AN6 Analog input channel 6 P57 AN7 P57 AN7 Analog input channel 7 Reference For the circuit type see Section 1...

Page 203: ...ters and pins for port 5 ADER Pin Pch Nch Analog input Output latch PDR Port data register DDR read DDR write DDR Port direction register PDR write PDR read Direction latch Standby control SPL 1 Standby control Control of stop mode SPL 1 timebase timer mode SPL 1 and clock mode SPL 1 Internal data bus Table 4 7 2 Correspondence between Registers and Pins for Port 5 Port Name Bits of Related Regist...

Page 204: ...ort 1 functions as an input port Analog input enable register ADER The analog input enable register ADER sets the general purpose I O ports and analog input pin in unit of ports When the ADE bit corresponding to the analog input pin is set to 1 port 5 functions as an analog input pin When the bit is set to 0 port 5 functions as a general purpose I O port Table 4 7 3 shows functions of the register...

Page 205: ...rt 5 direction register DDR5 0 The direction latch is 0 The output buffer is set to OFF and the pin becomes an input port pin R W 000015H 00000000B 1 The direction latch is 1 The output buffer is set to ON and the pin becomes an output port pin Analog input enable register ADER 0 General purpose I O ports R W 00001BH 11111111B 1 Analog input mode R W Read Write X Undefined Reference When using por...

Page 206: ...nd the pin enters the high impedance state When data is written to the port 5 data register PDR5 it is retained in the output latch in the PDR5 but not output to the pin When the PDR5 is read the level value Low or High of the pin is read Operation of analog input When using port 5 as an analog input pin set the bit in the ADER corresponding to the analog input pin to 1 Port 5 is disabled to opera...

Page 207: ...n the pin state specification bit of the low power consumption mode control register LPMCR SPL is 1 at a transition to the stop mode timebase timer mode or watch mode the pin enters the high impedance state The output buffer is set forcibly to OFF irrespective of the value of the DDR5 Table 4 7 4 shows the state of the port 5 pins Table 4 7 4 The state of the port 5 pins Pin Name Normal Operation ...

Page 208: ... name Applicable ports Function 0 Unused bits Write No effect on operation Read Read value undefined 1 IL1 P00 to P17 0 CMOS hysteresis level 1 Automotive level 2 IL2 P20 to P27 0 CMOS hysteresis level 1 Automotive level1 3 IL3 P30 to P33 P35 P36 1 P37 1 0 CMOS hysteresis level 1 CMOS Automotive level 4 IL4 P40 to P44 0 CMOS hysteresis level 1 Automotive level 5 IL5 P50 to P57 0 CMOS hysteresis le...

Page 209: ...timebase timer 5 1 Overview of Timebase Timer 5 2 Block Diagram of Timebase Timer 5 3 Configuration of Timebase Timer 5 4 Interrupt of Timebase Timer 5 5 Explanation of Operations of Timebase Timer Functions 5 6 Precautions when Using Timebase Timer 5 7 Program Example of Timebase Timer ...

Page 210: ...imer counter reaches the interval time set by the interval time select bits TBTC TBC1 TBC0 an overflow occurs TBTC TBOF 1 and an interrupt request is generated When an interrupt is enabled when an overflow occurs TBTC TBIE 1 an overflow occurs TBTC TBOF 1 and an interrupt is generated The timebase timer has four interval times that can be selected Table 5 1 1 shows the interval times of the timeba...

Page 211: ...y Clock Clock Cycle Oscillation Stabilization Wait Time 210 HCLK approx 256 µs 213 HCLK approx 2 0 ms 215 HCLK approx 8 2 ms 217 HCLK approx 32 8 ms Watchdog timer 212 HCLK approx 1 0 ms 214 HCLK approx 4 1 ms 216 HCLK approx 16 4 ms 219 HCLK approx 131 1 ms PPG timer 29 HCLK approx 128 µs HCLK Oscillation clock The parenthesized values are provided at 4 MHz oscillation clock As the oscillation cy...

Page 212: ...t number 16 10 H 21 HCLK Timebase timer counter To watchdog timer Interval timer selector To clock control part oscillation stabilization waiting time selector Counter clear circuit Power on reset Stop mode CKSCR MCS 1 0 1 CKSCR SCS 0 1 2 Timebase timer interrupt signal OF OF OF OF TBIE TBOF TBC1 TBC0 TBR Timebase timer control register TBTC TBOF set TBOF clear Reserved OF Over flow HCLK Oscillati...

Page 213: ...p mode or PLL stop mode CKSCR SCS 1 LPMCR STP 1 Switching the clock mode from main clock mode to PLL clock mode from subclock mode to PLL clock mode or from subclock mode to main clock mode Interval timer selector The time interval selector selects the output of the timebase timer counter from four types When incrementing causes the selected interval time bit to overflow an interrupt request is ge...

Page 214: ...r Generation of Interrupt Request from Timebase Timer When the selected timebase timer counter bit reaches the interval time the overflow interrupt request flag bit in the timebase timer control register TBTC TBOF is set to 1 If the overflow interrupt request flag bit is set TBTC TBOF 1 when the interrupt is enabled TBTC TBIE 1 the timebase timer generates an interrupt request 0 0 0 1 1 0 15 14 bi...

Page 215: ...prox 16 4ms 219 HCLK approx 131 1ms Interval time select bit bit9 bit8 TBIE 0 1 Disabling of over flow interrupt request Enabling of over flow interrupt request Over flow interrupt enable bit bit12 TBR Timebase timer counter clear bit HCLK Oscillation clock The parenthesized values are provided when the oscillation clock operates at 4 MHz 1 is always read Clear timebase timer counter Clear TBOF bi...

Page 216: ...urs with interrupts enabled TBIE 1 an interrupt request is generated When set to 0 The bit is cleared When set to 1 Disabled The state remains unchanged Read by read modify write instructions 1 read Note 1 To clear the TBOF bit disable interrupts TBIE 0 or mask interrupts using the interrupt mask register ILM in the processor status 2 The TBOF bit is cleared at a write of 0 transition to main stop...

Page 217: ...to 1 When the overflow interrupt request flag bit in the timebase timer control register is set TBTC TBOF 1 with an interrupt enabled TBTC TBIE 1 an interrupt request is generated When the selected interval time is reached the overflow interrupt request flag bit in the timebase timer control register TBTC TBOF is set regardless of whether an interrupt is enabled or disabled TBTC TBIE To clear the ...

Page 218: ... an interrupt at every set interval time The timebase timer continues incrementing in synchronization with the main clock a half frequency of the oscillation clock while the oscillation clock is active When the timebase timer counter reaches the interval time set by the interval time select bits in the timebase timer control register TBTC TBC1 TBC0 it causes an overflow carrying and the overflow i...

Page 219: ...ared to stop counting At return from the stop mode the timebase timer counts the oscillation stabilization wait time of the main clock Figure 5 5 2 Example of operation of timebase timer Start CPU operation Power on reset Clear by interrupt process Counter clear TBTC TBR 0 Interval cycle TBTC TBC1 TBC0 11B Counter value Clear by transfering to stop mode Oscillation stabilization waiting over flow ...

Page 220: ...ime of main clock completed watchdog reset None External reset None Software reset None Switching Clock Mode Main clock PLL clock CKSCR MCS 1 0 Transition to PLL clock mode after oscillation stabilization wait time of PLL clock completed Main clock sub clock CKSCR SCS 1 0 Transition to sub clock mode after oscillation stabilization wait time of sub clock completed Sub clock main clock CKSCR SCS 0 ...

Page 221: ... None Return to PLL clock mode None Cancellation of sleep modes Cancellation of main sleep mode None Cancellation of sub sleep mode None Cancellation of PLL sleep mode None Table 5 5 1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer 2 2 Operation Counter Clear TBOF Clear Oscillation Stabilization Wait Time Note Clearing the timebase timer counter may affect the operat...

Page 222: ...ain stop mode PLL stop mode and sub clock mode the oscillation clock stops Therefore when oscillation starts the timebase timer requires the oscillation stabilization wait time of the main clock An appropriate oscillation stabilization wait time must be selected according to the types of oscillators connected to high speed oscillation input pins Resources to which timebase timer supplies clock At ...

Page 223: ...DE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disable MOV I ICR02 00H Interrupt level 0 highest MOV I TBTC 10000000B Upper 3 bis are fixed TBOF clear Counter clear interval time 212 HCLK selection SETB I TBIE Interrupt enable MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H Interrupt enable LOOP MOV A 00H No limit roop MOV A 01H BRA LOOP Interrupt program WARI CLRB I...

Page 224: ...206 CHAPTER 5 Timebase timer ...

Page 225: ...d operation of the watchdog timer 6 1 Overview of Watchdog Timer 6 2 Configuration of Watchdog Timer 6 3 Watchdog Timer Registers 6 4 Explanation of Operations of Watchdog Timer Functions 6 5 Precautions when Using Watchdog Timer 6 6 Program Examples of Watchdog Timer ...

Page 226: ...erval time of the watchdog timer is set by the timebase timer output select bit watch timer output select bit in the watchdog timer control register WDTC WT1 WT0 Table 6 1 1 lists the interval times of the watchdog timer Table 6 1 1 Interval Time of Watchdog Timer Min Max Clock Cycle Min Max Clock Cycle Approx 3 58 ms Approx 4 61 ms 214 211 HCLK Approx 0 457 s Approx 0 576 s 212 29 SCLK Approx 14 ...

Page 227: ...LK 21 22 211 212 213 214 215 216 217 218 210 29 28 Timebase timer counter Watchdog reset generation circuit To internal reset generation circuit Start up Watchdog timer control register WDTC Watchdog timer 2 Clear Counter clear control circuit Generation of reset Shift to sleep mode Shift to stop mode SRST WT1 WT0 WTE HCLK Oscillation clock SCLK Sub clock PONR WRST ERST Count clock selector 2 bit ...

Page 228: ...se timer output or watch timer output as a count clock The clock source output destination is set by the watchdog clock select bit in the watch timer control register WTC WDCS Watchdog reset generator The watchdog reset generation circuit generates a reset signal when the watchdog timer overflows Counter clear circuit The counter clear controller clears the watchdog timer counter Watchdog timer co...

Page 229: ...is section explains the registers used for setting the watchdog timer List of Registers and Reset Values of Watchdog Timer Figure 6 3 1 List of Registers and Reset Values of Watchdog Timer 1 1 1 7 6 bit 5 4 3 2 1 0 Watchdog timer control register WDTC Undefined ...

Page 230: ...et write 1 to RST bit bit7 bit5 bit4 bit3 Reset value XXXXX111B 4 5 3 2 1 6 R R R R W W W 0 7 R Read only W Write only The previous state is held X Undefined WTE Watchdog timer control bit First programming after reset Start up the watchdog timer No effect Twice or more programming after reset Clear the watchdog timer 0 1 bit2 Interval time Clock cycle Min Max WT0 0 1 0 1 WT1 0 0 1 1 approx 0 457s...

Page 231: ... the watchdog timer is started is ignored These are write only bits bit2 WTE Watchdog timer control bit This bit starts or clears the watchdog timer When set to 0 first time after reset The watchdog timer is started When set to 0 second or subsequent The watchdog timer is cleared bit6 Unused bits Read The value is undefined Write No effect bit3 to bit7 PONR WRST ERST SRST Reset Factor Bit These bi...

Page 232: ...he bit is set to 0 the watch timer is selected After a reset the bit returns to 1 During operation in the sub clock mode set the WDCS bit to 0 to select the watch timer Setting interval time Set the interval time select bits WDTS WT1 WT0 to select the interval time for the watchdog timer Set the interval time concurrently when starting the watchdog timer Writing to the bit is ignored after the wat...

Page 233: ...me it overflows and the CPU is reset A reset or transitions to the standby modes sleep mode stop mode watch mode timebase timer mode clear the watchdog timer During operation in the timebase timer mode or watch mode the watchdog timer counter is cleared However the watchdog timer remains in the activation state Figure 6 4 2 shows relationship between clear timing and interval time of watch dog tim...

Page 234: ... of counter clock Watchdog timer block diagram Clock selector WTE bit clear WTE bit Reset signal Count enable and clear 2 bit counter Count start a b c d Counter clear Watchdog reset generation 7 Count clock cycle 2 2 division s value c Count enable Reset signal d 2 division s value b Count clock a Minimum interval time When clear WTE bit immediately after rising of counter clock WTE bit clear Cou...

Page 235: ... may become long Note that the timebase timer is cleared when 0 is written to the timebase timer counter clear bit TBR in the timebase timer control register TBTC and when the clock mode changes from the main clock to PLL clock from the subclock to main clock or from the subclock to PLL clock Set the interval time concurrently when starting the watchdog timer Setting the time interval except start...

Page 236: ...ust be executed once within the minimum interval time of the watchdog timer Coding example WTE EQU WDTC 2 Watchdog control bit Main program CODE CSEG START Stack pointer SP already initialized MOV I WDTC 00000011B Start up of watchdog timer Select interval time 221 218 cycle LOOP CLRB I WTE Clear watchdog timer User processing BRA LOOP Vector setting VECT CSEG ABS 0FFH ORG 00FFDCH Reset vector set...

Page 237: ...ut Timer 7 2 Block Diagram of 16 bit Input Output Timer 7 3 Configuration of 16 bit Input Output Timer 7 4 Interrupts of 16 bit Input Output Timer 7 5 Explanation of Operation of 16 bit Free run Timer 7 6 Explanation of Operation of Input Capture 7 7 Precautions when Using 16 bit Input Output Timer 7 8 Program Example of 16 bit Input Output Timer ...

Page 238: ...in the count value generates an interrupt Interrupt generation starts the extended intelligent I O service EI2OS Either a reset or software reset by the timer count clear bit TCCS CLR clears the count value of the 16 bit free run timer to 0000H The count value of the 16 bit free run timer is output to the input capture and can be used as the base time for capture operation Functions of input captu...

Page 239: ... bit Input Output Timer 16 bit free run timer The count value of the 16 bit free run timer can be use as the base time for the input capture Input capture The input capture detects the rising edge falling edge or both edges of the external signal input to the input pins to retain the count value of the 16 bit free run timer Detecting the edge of the input signal generates an interrupt Internal dat...

Page 240: ...r divides the frequency of the machine clock to supply a count clock to the 16 bit up counter Any of four machine clock division ratios are selected by setting the timer counter control status register TCCS Timer counter data register TCDT The timer counter data register TCDT is a 16 bit up counter At read the current count value of the 16 bit free run timer can be read Writing while the counter i...

Page 241: ...egister TCCS The timer counter control status register TCCS selects the division ratio of the machine clock clears the count value by software enables or disables the count operation checks and clears the overflow generation flag and enables or disables interrupt ...

Page 242: ... Input capture control status register ICS01 Edge detection circuit Input capture instruction request EG00 EG01 EG10 EG11 ICE0 ICE1 ICP0 ICP1 IN1 IN0 Input capture data register 3 IPCP3 Input capture data register 2 IPCP2 2 2 Input capture control status register ICS23 Pin Edge detection circuit Input capture data register 1 IPCP1 Input capture data register 0 IPCP0 2 2 EG00 EG01 EG10 EG11 ICE0 IC...

Page 243: ...e input capture control status registers start and stop the capture operation of each input capture check and clear the valid edge detection flag when the edge is detected and enable or disable an interrupt The ICS01 register sets the input capture corresponding to the input pins IN0 and IN1 and the ICS23 register sets the input capture corresponding to the input pins IN2 and IN3 Edge detection ci...

Page 244: ...am of Pins for 16 bit Input Output Timer Table 7 3 1 Pins of 16 bit Input Output Timer Pin Name Pin Function Pin Setting Required for Use of 16 bit Input Output Timer IN0 General purpose I O port capture input Set as input port in port direction register DDR IN1 General purpose I O port capture input Set as input port in port direction register DDR IN2 General purpose I O port capture input Set as...

Page 245: ... 9 15 8 14 13 12 11 10 9 15 8 Input capture control status register ICS01 bit 7 6 5 4 3 2 1 0 Input capture data register 0 upper IPCP0 H bit Input capture data register 0 lower IPCP0 L bit Input capture data register 1 upper IPCP1 H bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Input capture data register 1 lower IPCP1 L bit Input capture control status register ICS23 7 6 bit 5 4 3 2 1 0 In...

Page 246: ... control status register TCCS IVF is set to 1 When an overflow interrupt is enabled TCCS IVFE 1 an interrupt request is generated Edge detection by capture function The counter value of the 16 bit free run timer actually read when the edge of the external signal input to the input pins IN0 to IN3 is detected is stored in the input capture data registers IPC0 to IPC3 corresponding to the input pins...

Page 247: ...sure to set to 0 bit4 STOP 0 1 Timer count operating bit Count operating enabled Count operating disabled stop bit5 CLK2 CLK1 bit1 bit2 φ Machine clock Read Write Reset value R W IVF Over flow generating flag bit Without over flow IVFE 0 1 Over flow interrupt enable bit Over flow interrupt disabled Over flow interrupt enabled bit6 CLK0 bit0 Count clock φ φ 2 φ 4 φ 8 φ 16 φ 32 φ 64 φ 128 φ 16MHz 62...

Page 248: ...disables stops the count operation of the 16 bit free run timer When set to 0 Enables count operation The 16 bit timer counter data register TCDT starts incrementing in synchronization with the count clock selected by the count clock select bits CLK1 and CLK0 When set to 1 Stops count operation bit6 IVFE Overflow interrupt enable bit This bit enables or disables an interrupt request generated when...

Page 249: ...CCS IVF is also set to 1 When an overflow occurs TCCS IVF 1 with an overflow interrupt enabled TCCS IVFE 1 an overflow interrupt request is generated The count value of the timer counter data register TCDT is retained while the count operation is stopped When stopping the count operation of the timer counter data register TCDT write 1 to the timer count operation bit TCCS STOP When the count opera...

Page 250: ...register in synchronization with the count clock and each of the other events clears the register on occurrence of that event Reset Writing 1 to the timer count clear bit TCCS CLR possible even during count operation Writing 0000H to timer counter data register TCDT while count operation stopped Overflow in 16 bit free run timer Note Always use a word instruction MOVW to set the timer counter data...

Page 251: ...2 interrupt disable Input capture 0 2 interrupt enable bit4 bit6 ICE1 0 1 Input capture 1 3 interrupt enable bit Input capture 1 3 interrupt disable Input capture 1 3 interrupt enable bit5 EG01 0 0 1 1 EG00 0 1 0 1 bit0 Input capture 0 2 edge select bit bit1 Input capture 0 2 enable available edge detection flag bit ICP0 Read Write Input capture 0 2 without available edge detection Clear of ICP0 b...

Page 252: ... ICE1 Input capture 1 interrupt enable bit This bit enables or disables an interrupt when the edge is detected by input capture 1 When set to 0 No interrupt is generated even when the edge is detected by input capture 1 When set to 1 An interrupt is generated when the edge is detected by input capture 1 bit6 ICP0 Input capture 0 valid edge detection flag bit This bit indicates the edge detection b...

Page 253: ...apture Data Registers 0 to 3 IPCP0 to IPCP3 At the same time that the edges of signals input from the input pins IN0 to IN3 of the 16 bit input output timer are detected the counter value of the 16 bit free run timer is stored in the input capture data registers 0 to 3 IPCP0 to IPCP3 corresponding to the input pins INO to IN3 R R R R R R R R CP11 CP9 CP10 CP12 CP13 CP14 R R R R R R R R CP3 CP1 CP2...

Page 254: ...s IN0 to IN3 are set to 1 When the valid edge is detected by the input captures corresponding to the input pins IN0 to IN3 with the input capture interrupts corresponding to the input pins IN0 to IN3 enabled an input capture interrupt is generated Correspondence between 16 bit Input Output Timer Interrupt and EI2OS For details of the interrupt number interrupt control register and interrupt vector...

Page 255: ...ed from FFFFH to 0000H an overflow occurs When an overflow occurs the overflow generation flag bit TCCS IVF is set to 1 and the 16 bit free run timer starts incrementing again from 0000H When an overflow occurs TCCS IVF 1 with an overflow interrupt enabled TCCS IVFE 1 an overflow interrupt request is generated When stopping the count operation of the timer counter data register TCDT write 1 to the...

Page 256: ...er Operation Timing of 16 bit Free run Timer Figure 7 5 2 shows counter clearing at an overflow Figure 7 5 2 Counter Clearing at an Overflow Reset Counter value Time FFFFH BFFFH 7FFFH 3FFFH 0 0 0 0 H Over flow Over flow interrupt ...

Page 257: ... in the input capture data registers Setting of Input Capture Operation of the input capture requires the setting shown in Figure 7 6 1 Figure 7 6 1 Setting of Input Capture ICE0 EG11 EG01 EG00 EG10 ICP1ICP0 ICE1 IPCP ICS bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 Hold counter value of 16 bit free run timer Setting the corresponding bit using pin as capture input pin to 0 Using bit DDR port...

Page 258: ... EG When the effective edge is detected by the input captures corresponding to the input pins IN0 to IN3 when the input captures corresponding to the input pins IN0 to IN3 are enabled for interrupts an input capture interrupt is generated The input capture valid edge detection flag bit ICS ICP is set when the valid edge is detected regardless of the interrupt enable settings ICS01 ICS23 ICE1 ICE0 ...

Page 259: ...ding on Edge Type Counter value Capture signal φ Input capture input Input capture data register IPCP N N 1 Available edge N 1 Input capture interrupt Capturing counter value Machine clock φ Reset Counter value Time IN1 falling edge IN0 rising edge IN2 both edge FFFFH BFFFH 7 F F F H 3 F F F H 0 0 0 0 H Undefined Undefined Undefined 7FFFH 3FFFH BFFFH 3FFFH Input capture data register 0 IPCP0 input...

Page 260: ... interrupts When an overflow interrupt or an input capture interrupt is enabled clear only the set bit of the overflow generation flag bit or the input capture valid edge detection flag bit When clearing the flag bit for an event that caused an interrupt to be accepted for example avoid unconditional clearing of the interrupt request flag bits for other interrupt trigger events because another inp...

Page 261: ...an be determined from the following equation Cycle overflow count x 10000H nth IPCP0 value n 1 th IPCP0 value x count clock cycle overflow count x 10000H nth IPCP0 value n 1 th IPCP0 value x 0 25 µs Coding example DDR1 EQU 000011H Port direction register TCCS EQU 000058H Timer counter control Status register TCDT EQU 000056H Timer counter data register ICS01 EQU 000054H Input capture control Statu...

Page 262: ...vel Interrupt enable OR CCR 40H Interrupt enanle Interrupt program WARI1 CLRB I ICP0 Input capture 0 interrupt request Flag clear User processing processing of cycle calculate MOV A 0 Over flow for next cycle measuring Clear counter MOV D OV_CNT A RETI Recover from interrupt WARI2 CLRB I IVFE Clear over flow interrupt request flag INC D OV_CNT Over flow counter incremented by one RETI CODE ENDS Ve...

Page 263: ...d timer 8 1 Overview of 16 bit Reload Timer 8 2 Block Diagram of 16 bit Reload Timer 8 3 Configuration of 16 bit Reload Timer 8 4 Interrupts of 16 bit Reload Timer 8 5 Explanation of Operation of 16 bit Reload Timer 8 6 Precautions when Using 16 bit Reload Timer 8 7 Program Example of 16 bit Reload Timer ...

Page 264: ...90895 series has two channels of 16 bit reload timers Operation Modes of 16 bit Reload Timer Table 8 1 1 indicates the operation modes of the 16 bit reload timer Internal clock mode When the count clock select bits in the timer control status register TMCSR CSL1 CSL0 are set to 00B 01B or 10B the 16 bit reload timer is set in the internal clock mode In the internal clock mode the 16 bit reload tim...

Page 265: ... 16 bit reload timer is set to the event count mode In the event count mode the 16 bit reload timer decrements in synchronization with the edge detection of the external event clock input to the TIN pin A software trigger is selected as the start trigger The 16 bit reload timer can be used as an interval timer by using a fixed cycle of the external clock ...

Page 266: ...it in the timer control status register TMCSR OUTL can be set to select the level High or Low of the rectangular wave Reload mode TMCSR RELD 1 When an underflow occurs the value set in the TMRLR is reloaded to the TMR continuing the TMR count operation In the reload mode a toggle wave inverting the output level of the TOT pin is output each time an underflow occurs during the TMR count operation T...

Page 267: ...mer Timer control status register TMCSR Prescaler CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG MOD0 Internal data bus Input control circuit Clock selector Valid clock judge circuit 16 bit reload register 16 bit timer register UF Machine clock Interrupt request output Pin Pin φ Reload control circuit Output signal generating circuit Operating control circuit TMR TMRLR Count clock generating ...

Page 268: ... the machine clock or external event clock Reload controller When the 16 bit reload timer starts operation or the TMR underflows the reload controller reloads the value set in the 16 bit reload register TMRLR to the TMR Output controller The output controller inverts and enables or disables the output of the TOT pin at underflow Operation controller The operation controller starts or stops the 16 ...

Page 269: ...control status register TMCSR selects the operation mode sets the operation conditions selects the start trigger performs a start using the software trigger selects the reload operation mode enables or disables an interrupt request sets TOT pin output level and sets TOT output pin ...

Page 270: ...bit Reload Timer Table 8 3 1 Pins of 16 bit Reload Timer Pin Name Pin Function Pin Setting Required for Use in 16 bit Reload Timer TIN0 General purpose I O port 16 bit reload timer input Set as input port in port direction register DDR TOT0 General purpose I O port 16 bit reload timer output Set timer output enable TMCSR0 OUTE 1 TIN1 General purpose I O port 16 bit reload timer input Set as input ...

Page 271: ...bit 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16 bit timer register upper TMR0 15 14 bit 13 12 11 10 9 8 16 timer register lower TMR0 bit 7 6 5 4 3 2 1 0 15 14 bit 13 12 11 10 9 8 bit 16 bit reload register upper TMRLR0 16 bit reload register lower TMRLR0 Undefined 0 0 0 0 Timer control status register upper TMCSR1 15 14 bit 13 12 11 10 9 8 0 0 0 0 0 Timer control status register lower TMCSR1 0 0 0 7 6 bit 5 4 ...

Page 272: ...t reload timer is started and the count value of the 16 bit timer register is decremented from 0000H to FFFFH an underflow occurs When an underflow occurs the UF bit in the timer control status register is set to 1 TMCSR UF If an underflow interrupt is enabled TMCSR INTE 1 an interrupt request is generated ...

Page 273: ...e CSL1 0 00B 01B 10B 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 Input pin function T Machine cycle 12 13 11 10 9 8 bit9 bit8 bit7 MOD2 MOD1 MOD0 Operating mode select bit Event count mode CSL1 0 11B Rising edge 0 0 1 1 0 1 0 1 Input pin function Valid edge bit9 bit8 bit7 CSL1 CSL0 Count clock select bit Internal clock mode 21T 23T 25 T 0 0 1 1 0 1 0 1 Count clock Count clock cycle bit11 bit10 14 Reset value ...

Page 274: ...operation of the TMR When MOD2 set to 1 The input pin functions as a gate input The MOD1 bit is not used The MOD0 bit is used to select the signal level High or Low to be detected The count operation of the 16 bit timer register TMR is performed only when the signal level is input Event count mode The MOD2 bit is not used An external event clock is input from the input pin The MOD1 and MOD0 bits a...

Page 275: ...LD 0 1 One shot mode Reload mode Reload select bit bit4 UF Under flow generating flag bit Without under flow Clear UF bit 0 1 Read Write bit2 OUTL TOT pin output level select bit One shot mode RELD 0 Reloaad mode RELD 1 bit5 bit6 Pin function General purpose I O port General purpose I O port General purpose I O port Register and pin support for channel TOT pin output enable bit OUTE 0 1 Reset valu...

Page 276: ... instructions 1 read bi3 INTE Underflow interrupt enable bit This bit enables or disables an under flow interrupt When an underflow occurs TMCSR UF 1 with an underflow interrupt enabled TMCSR INTE 1 an interrupt request is generated bit4 RELD Reload select bit This bit sets the reload operation at underflow When set to 1 At underflow reloads value set in TMRLR to TMR continuing count operation rel...

Page 277: ... TMR count operation an underflow occurs Reload mode When the TMR underflows the value set in the TMRLR is reloaded to the TMR starting the TMR count operation One shot mode When the TMR underflows the TMR count operation is stopped entering the start trigger input wait state The TMR value is retained to FFFFH R R R R R R R R D11 D8 D9 D10 D15 D12 D13 D14 R R R R R R R R D3 D0 D1 D2 D7 D4 D5 D6 15...

Page 278: ...e timer operation TMCSR CNTE 1 When the start trigger is input the value set in the TMRLR is reloaded to the TMR starting the TMR count operation W W W W W W W W D11 D8 D9 D10 D15 D12 D13 D14 W W W W W W W W D3 D0 D1 D2 D7 D4 D5 D6 XXXXXXXXB XXXXXXXXB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset value Reset value Write only W Undefined X TMRLR0 TMRLR1 TMRLR0 TMRLR1 Notes Perform a write to the TMRL...

Page 279: ...d timer corresponds to the EI2 OS function An underflow in the TMR starts the EI2 OS Note however that EI2 OS can be used only when any other peripheral resources sharing the interrupt control register ICR is not using interrupts When using the EI2 OS in the 16 bit reload timers 0 and 1 it is necessary to disable generation of interrupt requests by resources sharing the interrupt control register ...

Page 280: ...al event to operate the 16 bit reload timer requires the setting shown in Figure 8 5 2 Figure 8 5 2 Setting of Event Count Mode TMCSR Other than 11B 1 Setting reload value to 16 bit timer register TMRLR CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG MOD0 11 10 9 8 5 6 4 3 2 1 7 14 13 12 bit0 bit15 Setting to 1 1 Using bit TMCSR 1 1 1 TMRLR CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG M...

Page 281: ...e CNTE 0 WAIT 1 TIN pin Input disabled TOT pin General purpose I O port LOAD CNTE 1 WAIT 0 Load the contents of 16 bit reload register to 16 bit timer register 16 bit timer register Hold value at stop A time until loading the value is undefined WAIT state CNTE 1 WAIT 1 TIN pin Valid for trigger input only TOT pin Output value of 16 bit reload register 16 bit timer register Operation RUN state CNTE...

Page 282: ...reload timer TMRLR is set to the internal clock mode In the internal clock mode the 16 bit timer register TMR decrements in synchronization with the internal clock In the internal clock mode three count clock cycles can be selected by setting the count clock select bits in the timer control status register TMCSR CSL1 CSL0 Setting a reload value to TMR After the 16 bit reload timer is started the v...

Page 283: ...the 16 bit reload timer register TMRLR is reloaded to the TMR continuing the TMR count operation In the reload mode a toggle wave inverting the output level of the TOT pin is output each time an underflow occurs during the TMR count operation The pin output level select bit in the timer control status register TMCSR OUTL can be set to select the level High or Low of a toggle wave as the 16 bit rel...

Page 284: ...t Reload data TRG bit 0000H TOT pin T 1 FFFFH Reload data 0000H 1 FFFFH Activating trigger input waite T Machine cycle It takes 1T time from trigger input to loading data of reload register Count clock Counter Data load signal CNTE bit UF bit Reload data TRG bit 0000H Reload data 0000H Reload data 0000H Reload data TOT pin T 1 1 1 1 T Machine cycle It takes 1T time from trigger input to loading da...

Page 285: ...8 5 6 Count Operation in External Trigger Mode One shot Mode Figure 8 5 7 Count Operation in External Trigger Mode Reload Mode Note The trigger pulse width of the edge to be input to the TIN pin should be 2 machine cycles time or more 0000H 1 FFFFH 0000H 1 FFFFH 2T to 2 5T Count clock Counter Data load signal CNTE bit UF bit Reload data TIN bit TOT pin Activating trigger input waite T Machine cycl...

Page 286: ...input level High or Low can be selected by setting the operation mode select bits in the timer control status register TMCSR MOD2 to MOD0 Figure 8 5 8 Count Operation in External Gate Input Mode One shot Mode Figure 8 5 9 Count Operation in External Gate Input Mode Reload Mode Reload data 0000H T 1 1 1 1 FFFFH T Count clock Counter Data load signal CNTE bit UF bit Reload data TRG bit TOT pin Activ...

Page 287: ...t mode by setting the count clock select bits in the timer control status register TMCSR CSL1 CSL0 to 11B In the event count mode the TMR decrements in synchronization with the edge detection of the external event clock input to the TIN pin Setting initial value of counter After the 16 bit reload timer is started the value set in the TMRLR is reloaded to the TMR 1 Disables the operation of the 16 ...

Page 288: ...is stopped entering the start trigger input wait state When the next start trigger is input the TMR count operation is restarted In the one shot mode a rectangular wave is output from the TOT pin during the TMR count operation The pin output level select bit in the timer control status register TMCSR OUTL can be set to select the level High or Low of a rectangular wave Reload mode TMCSR RELD 1 Whe...

Page 289: ...eration mode select bits in the timer control status register TMCSR MOD2 to MOD0 the detected edge can be selected from the rising edge falling edge and both edges Figure 8 5 10 Count Operation in Event Count Mode One shot Mode Figure 8 5 11 Count Operation in Event Count Mode Reload Mode Note The level width of the external event clock signal input to the TIN pin should be at least 4 T T machine ...

Page 290: ... count operation However always use the word instruction MOVW Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation TMCSR CNTE 0 Precautions on interrupt When the UF bit in the TMCSR is set to 1 and the underflow interrupt output is enabled TMCSR INTE 1 it is impossible to return from interrupt processing However when the EI2OS is used the UF bit is cleared automatically W...

Page 291: ...t reload timer Interrupt control register TMCSR0 EQU 000066H Timer control status register TMR0 EQU 003900H 16 bit timer register TMRLR0 EQU 003900H 16 bit reload register UF0 EQU TMCSR0 2 Interrupt request flag bit CNTE0 EQU TMCSR0 1 Counter operation enable bit TRG0 EQU TMCSR0 0 Software trigger bit Main program CODE CSEG Stack pointer sp already initialized AND CCR 0BFH Interrupt disabled MOV I...

Page 292: ...CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FFB8H Setting vector to interrupt 17 DSL WARI ORG 00FFDCH Reset vector setting DSL START DB 00H Setting to single chip mode VECT ENDS END START ICR03 EQU 0000B3H For 16 bit reload timer Interrupt control register TMCSR0 EQU 000066H Timer control status register TMR0 EQU 003900H 16 bit timer register TMRLR0 EQU 003900H 16 bit reload register DDR2 EQ...

Page 293: ... One shot mode selection interru Clear interrupt flag count star MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H Interrupt enabled LOOP User processing BRA LOOP Interrupt program WARI CLR I UF0 Clear interrupt request flag User processing RETI Recovery from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FFB8H Setting vector to interrupt 17 DSL WARI ORG 00FFDCH Reset vector setting...

Page 294: ...276 CHAPTER 8 16 bit reload timer ...

Page 295: ...s the functions and operations of the watch timer 9 1 Overview of Watch Timer 9 2 Block Diagram of Watch Timer 9 3 Configuration of Watch Timer 9 4 Watch Timer Interrupt 9 5 Explanation of Operation of Watch Timer 9 6 Program Example of Watch Timer ...

Page 296: ...erval time select bits WTC WTC2 to WTC0 the bit corresponding to the interval time of the watch timer counter overflows carries and the overflow flag bit is set WTC WTOF 1 When the overflow flag bit is set WTC WTOF 1 with interrupt enabled when an overflow occurs WTC WTIE 1 an interrupt request is generated The interval time of the watch timer can be selected from seven types The interval time of ...

Page 297: ...ws the cycles of clocks supplied from the watch timer Table 9 1 2 Cycle of Clock Supply from Watch Timer Receiver of clock supply Clock Cycle Timer for oscillation stabilization wait time of sub clock 214 SCLK 2 000s Watchdog timer 210 SCLK 125ms 213 SCLK 1 000s 214 SCLK 2 000s 215 SCLK 4 000s SCLK Sub clock frequency The parenthesized values are provided when the sub clock operates at 8 192 kHz ...

Page 298: ...imer counter The watch timer counter is a 15 bit up counter that uses the sub clock SCLK as a count clock Counter clear circuit The counter clear circuit clears the watch timer counter Watch timer counter To watchdog timer Interval timer selector Counter clear circuit Power on reset Stop mode transmission Watch timer interrupt WTOF WTR WTC1 WTC0 WTC2 WDCS SCE WTIE 25 24 23 21 29 210 211 212 213 21...

Page 299: ...the watch timer counter reaches the interval time set in the watch timer control register WTC Watch timer control register WTC The watch timer control register WTC selects the interval time clears the watch timer counter enables or disables an interrupt checks the overflow state and clears the overflow flag bit ...

Page 300: ...f Watch Timer Generation of Interrupt Request from Watch Timer When the interval time set by the interval time select bits WTC WTC2 to WTC0 is reached the overflow flag bit WTC WTOF is set to 1 When the overflow flag bit is set WTC WTOF 1 and with interrupt enabled when the watch timer counter overflows carries WTC WTIE 1 an interrupt request is generated 0 0 0 Watch timer control register WTC 0 0...

Page 301: ...CLK 250ms 212 SCLK 500ms 213 SCLK 1 0s 214 SCLK 2 0s 215 SCLK 4 0s WTC1 0 0 1 1 0 0 1 1 bit1 WTC0 0 1 0 1 0 1 0 1 bit0 Undefined X Subclock Reset value SCLK The values in are the calculated example at subclock 8 192 kHz Read only R Read Write R W Watch timer clear bit WTR Read Clear watch timer counter bit3 0 1 Watchdog clock select bit Input clock of watchdog timer WDCS Watch timer Set 0 bit7 0 1...

Page 302: ...its WTC2 to WTC0 overflows bit5 WTIE Overflow interrupt enable bit This bit enables or disables generation of an interrupt request when the watch timer counter overflows carries When set to 0 Interrupt request not generated even at overflow WTOF 1 When set to 1 Interrupt request generated at overflow WTOF 1 bit6 SCE Oscillation stabilization wait time end bit This bit indicates that the oscillatio...

Page 303: ...register is set to 1 WTC WTOF 1 When the overflow flag bit is set WTC WTOF 1 with the watch timer interrupt enabled WTC WTIE 1 an interrupt request is generated At interrupt processing set the WTOF bit to 0 and cancel the interrupt request Watch Timer Interrupt and EI2OS Function The watch timer does not correspond to the EI2OS function For details of the interrupt number interrupt control registe...

Page 304: ...imer as an interval timer requires the settings shown in Figure 9 5 1 Figure 9 5 1 Setting of Watch Timer When the value set by the interval time select bits WTC1 WTC0 in the watch timer control register WTC is reached the overflow flag bit in the WTC register is set to 1 WTC WTOF 1 When the overflow flag bit is set WTC WTOF 1 with the overflow interrupt of the watch timer counter enabled WTC WTIE...

Page 305: ...ing Setting Operation Clock of Watchdog Timer The watchdog clock select bit WDCS in the watch timer control register WTC can be used to set the clock input source of the watchdog timer When using the sub clock as the machine clock always set the WDCS bit to 0 and select the output of the watch timer Oscillation Stabilization Wait Time Timer of Sub clock When the watch timer returns from the power ...

Page 306: ...t Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disabled MOV I ICR07 00H Interrupt level 0 storngest MOV I WTC 10100101B Interrupt enabled Clear over flow flag Clear watch timer caunter 213 SCLK approx 1 0s MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H Interrupt enabled LOOP User processing BRA LOOP Interrupt program WARI CLRB I WTOF Clear over flow...

Page 307: ...ons of the 8 16 bit PPG timer 10 1 Overview of 8 16 bit PPG Timer 10 2 Block Diagram of 8 16 bit PPG Timer 10 3 Configuration of 8 16 bit PPG Timer 10 4 Interrupts of 8 16 bit PPG Timer 10 5 Explanation of Operation of 8 16 bit PPG Timer 10 6 Precautions when Using 8 16 bit PPG Timer ...

Page 308: ...ection explains the functions of PPG0 1 PPG2 3 has the same functions as PPG0 1 Functions of 8 16 bit PPG Timer The 8 16 bit PPG timer consists of four eight bit reload registers PRLH0 PRLL0 PRLH1 PRLL1 and two PPG down counters PCNT0 PCNT1 Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty ratio The count clock can be selected from six internal...

Page 309: ...Time Output Pulse Time 1 φ 62 5ns 1 φ to 28 φ 2 to 29 φ 2 φ 125ns 2 φ to 29 φ 22 to 210 φ 22 φ 250ns 22 φ to 210 φ 23 φ to 211 φ 23 φ 500ns 23 φ to 211 φ 24 φ to 212 φ 24 φ 1µs 24 φ to 212 φ 25 φ to 213 φ 29 HCLK 128µs 29 HCLK to 217 HCLK 210 HCLK to 218 HCLK HCLK Oscillation clock φ Machine clock The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine cl...

Page 310: ...PPG1 Interval Time Output Pulse Time Interval Time Output Pulse Time 1 φ 62 5ns 1 φ to 28 φ 2 φ to 29 φ 1 φ to 216 φ 2 φ to 217 φ 2 φ 125ns 2 φ to 29 φ 22 φ to 210 φ 2 φ to 217 φ 22 φ to 218 φ 22 φ 250ns 22 φ to 210 φ 23 φ to 211 φ 22 φ to 218 φ 23 φ to 219 φ 23 φ 500ns 23 φ to 211 φ 24 φ to 212 φ 23 φ to 219 φ 24 φ to 220 φ 24 φ 1µs 24 φ to 212 φ 25 φ to 213 φ 24 φ to 220 φ 25 φ to 221 φ 29 HCLK ...

Page 311: ...diagrams for the 8 16 bit PPG timer 0 and 8 16 bit PPG timer 1 The PPG2 has the same function as the PPG0 and PPG3 has the same function as PPG1 Channels and PPG Pins of PPG Timers Figure 10 2 2 shows the relationship between the channels and the PPG pins of the 8 16 bit PPG timers in the MB90895 series Figure 10 2 1 Channels and PPG Pins of PPG Timers PPG0 1 Pin PPG0 output pin Pin PPG1 output pi...

Page 312: ...l clock 1 φ Peripheral clock 2 φ Peripheral clock 4 φ Peripheral clock 8 φ Peripheral clock 16 φ Pin PPG0 Interrupt request output Reload Select signal Count starting value Inversion PPG output control circuit Clear Pulse selector Operating mode control signal PPG0 reload register Under flow CLK Select signal PPG1 under flow PPG0 under flow to PPG1 R S Q Count clock selector PEN0 PE0 PIE0 PUF0 Res...

Page 313: ...verted when underflow occurs This counter is concatenated for use as a single channel 16 bit PPG down counter PPG0 temporary buffer PRLBH0 This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers PRLH0 and PRLL0 This buffer stores the PRLH0 value temporarily and enables it in synchronization with the timing of writing to the PRLL0 Reload register L H s...

Page 314: ...put control circuit Clear PPG1 reload register Under flow CLK MD0 Select signal PPG0 under flow from PPG0 Operating mode control signal PPG1 under flow to PPG0 R S Q Count clock selector PEN1 PE1 PIE1 PUF1 MD1 MD0 Reserved PPG0 1 count clock select register PPG01 Time base timer output 512 HCLK Peripheral clock 1 φ Peripheral clock 2 φ Peripheral clock 4 φ Peripheral clock 8 φ Peripheral clock 16 ...

Page 315: ... 8 bit down counter that alternately reloads the values set in the PPG1 reload registers PRLH1 and PRLL1 and counts down The pin output is inverted when underflow occurs This counter is concatenated for use as a single channel 16 bit PPG down counter PPG1 temporary buffer PRLBH1 This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers PRLH1 and PRLL1 I...

Page 316: ...298 CHAPTER 10 8 16 bit PPG timer PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs ...

Page 317: ... 10 3 1 Pins of 8 16 bit PPG Timer Channel Pin Name Pin Function Pin Setting Required for Use of 8 16 bit PPG Timer PPG0 PPG0 output pin General purpose I O ports PPG0 output pin Set PPG0 pin output to enabled PPGC0 PE0 1 PPG1 PPG1 output pin General purpose I O ports PPG1 output pin Set PPG1 pin output to enabled PPGC1 PE1 1 PPG2 PPG2 output pin General purpose I O ports PPG2 output pin Set PPG2 ...

Page 318: ... interrupts of channels causing an underflow are enabled PPGC0 PIF0 PPGC1 PIF1 an underflow interrupt request is generated to the interrupt controller PPG1 reload register H PRLH1 15 14 bit 13 12 11 10 9 8 PPG1 reload register L PRLL1 7 6 bit 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 PPG0 reload register H PRLH0 15 14 bit 13 12 11 10 9 8 PPG0 reload register L PRLL0 bit 0 1 0 0 0 PPG0 operating ...

Page 319: ...de Control Register PPGC0 Reset value 0 X 0 0 0 X X 1 B 4 5 3 2 1 7 6 0 Under flow generating flag bit PUF0 Read Write Without under flow Clear PUF0 bit bit3 0 1 PIE0 Under flow interrupt enable bit Interrupt request disabled bit4 0 1 PE0 PPG0 pin output enable bit General purpose I O port pulse output disabled bit5 0 1 PEN0 PPG0 operating enable bit Count operating disabled holding L level output...

Page 320: ...set to 0 The bit is cleared When the bit is set to 1 No effect Read by read modify write instructions 1 read bit4 PIE0 Underflow interrupt enable bit This bit enables or disables an interrupt When set to 0 No interrupt request generated even at underflow PUF0 1 When set to 1 Interrupt request generated at underflow PUF0 1 bit5 PE0 PPG0 pin output enable bit This bit switches the PPG0 pin function ...

Page 321: ...UF1 Read Write Without under flow Clear PUF1 bit bit11 0 1 PIE1 Under flow interrupt enable bit Under flow interrupt request disabled bit12 0 1 PE1 PPG1 pin output enable bit General purpose I O port pulse output disabled bit13 0 1 PEN1 PPG1 operating enabled Count operating disabled holding L level output bit15 0 1 Operating mode select bit MD1 8 bit PPG output 2ch independent operating mode bit1...

Page 322: ...rom 0000H to FFFFH an underflow occurs PUF1 1 When an underflow occurs PUF1 1 with an underflow interrupt enabled PIE1 1 an interrupt request is generated When set to 0 The bit is cleared When the bit is set to 1 No effect Read by read modify write instructions 1 read bit12 PIE1 Underflow interrupt enable bit This bit enables or disables an interrupt When set to 0 No interrupt request is generated...

Page 323: ... bit 1 φ 62 5ns 2 φ 125ns 22 φ 250ns 23 φ 500ns 24 φ 1 µs Setting disabled Setting disabled 29 HCLK 128 µs bit4 bit3 bit2 0 0 0 0 1 1 1 1 PCM1 0 0 1 1 0 0 1 1 PCM0 0 1 0 1 0 1 0 1 PCS2 PPG1 counter clock select bit 1 φ 62 5ns 2 φ 125ns 22 φ 250ns 23 φ 500ns 24 φ 1 µs Setting disabled Setting disabled 29 HCLK 128 µs bit7 bit6 bit5 0 0 0 0 1 1 1 1 PCS1 0 0 1 1 0 0 1 1 PCS0 0 1 0 1 0 1 0 1 R W R W R ...

Page 324: ...lected from five frequency divided clocks of the machine clock and the frequency divided clocks of the timebase timer bit5 to bit7 PCS2 to PCS0 PPG1 count clock select bits These bits set the count clock of the 8 16 bit PPG timer 1 The count clock can be selected from five frequency divided clocks of the machine clock and the frequency divided clocks of the timebase timer The settings of the PPG1 ...

Page 325: ... bit3 bit2 bit1 bit0 Reset value XXXXXXXXB Read Write R W Undefined X PRLH0 PRLH1 PRLL0 PRLL1 Table 10 3 5 Functions of PPG Reload Registers Function 8 16 bit PPG Timer 0 8 16 bit PPG Timer 1 Retains reload value on Low level side PRLL0 PRLL1 Retains reload value on High level side PRLH0 PRLH1 Notes In the 16 bit PPG output operation mode PPGC1 MD1 MD0 11B use a long word instruction to set the PP...

Page 326: ...r PPGC1 PIE1 1 an interrupt request is generated 16 bit PPG output operation mode In the 16 bit PPG output operation mode when the values of the PPG0 and PPG1 down counters are decremented from 0000H to FFFFH an underflow occurs When an underflow occurs the underflow generation flag bits in the two channels are set at one time PPGC0 PUF0 1 and PPGC1 PUF1 1 When an underflow occurs with either of t...

Page 327: ... vector address see 3 5 Interrupt 8 16 bit PPG Timer Interrupt and EI2OS Function The 8 16 bit PPG timer corresponds to the EI2 OS function Generation of an enabled interrupt factor starts the EI2OS However it is necessary to disable generation of interrupt requests by resources sharing the interrupt control register ICR with the 8 16 bit PPG timer ...

Page 328: ...If the values set in the reload registers are reloaded to the PPG down counters when an underflow occurs the pin output is inverted Figure 10 5 1 shows the output waveform of the 8 16 bit PPG timer Figure 10 5 1 Output Waveform of 8 16 bit PPG Timer Operation Modes of 8 16 bit PPG Timer As long as the operation of the 8 16 bit PPG timer is enabled PPGC0 PEN0 1 PPGC1 PEN1 1 a pulse waveform is outp...

Page 329: ...r PRLL0 PRLH0 PRLL1 PRLH1 and PPG timer operation is enabled PPGC0 PEN0 1 PPGC1 PEN1 1 the PPG down counter starts count operation in the channel that enables operation To stop the count operation of the PPG down counter disable the operation of the PPG timer of the channel to be stopped PPGC0 PEN0 0 PPGC1 PEN1 0 The count operation of the PPG down counter is stopped and the output of the PPG outp...

Page 330: ...oad register is 00 H the pulse width has one count clock cycle and if the value is FF H the pulse width has 256 count clock cycles The equations for calculating the pulse width are shown below PL T L 1 PH T H 1 PL Low width of output pulse PH High width of output pulse L Values of 8 bits in PPG reload register PRLL0 or PRLL1 H Values of 8 bits in PPG reload register PRLH0 or PRLH1 T Count clock cy...

Page 331: ...to set the values in the PPG reload registers or a word instruction to set the PPG0 and PPG1 PRLL0 PRLL1 or PRLH0 PRLH1 in this order PIE1 PUF1 MD0 Re served MD1 PEN1 PE1 PPGC1 PPGC0 1 1 1 1 1 PIE0 PUF0 Re served PEN0 PE0 PPG01 PCM2 PCM1 PCM0 PCS2 PCS1 PCS0 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 PRLH0 PRLL0 PRLH1 PRLL1 Reserved area 1 0 1 X Settting reload value lower 8 bits of PPG0 H l...

Page 332: ... the PPG1 down counter underflows the reload values set in the PPG0 and PPG1 reload registers PRLL0 PRLH0 and PRLL1 PRLH1 are reloaded simultaneously to the PPG down counters PCNT0 PCNT1 When an underflow occurs the underflow generation flag bits in both channels are set simultaneously PPGC0 PUF0 1 PPGC1 PUF1 1 If an interrupt request is enabled at either channel PPGC0 PIE0 1 PPGC1 PIE1 1 an inter...

Page 333: ... equations for calculating the pulse width are shown below PL T L 1 PH T H 1 PL Low width of output pulse PH High width of output pulse L Values of 16 bits in PPG reload register PRLL0 PRLL1 H Values of 16 bits in PPG reload register PRLH0 PRLH1 T Count clock cycle Figure 10 5 5 shows the output waveform in the 8 8 bit PPG output operation mode Figure 10 5 5 Output waveform in 16 bit PPG output op...

Page 334: ...eration Mode Note Use the word instruction to set both High level and Low level PPG reload registers PRLL0 PRLH0 and PRLL1 PRLH1 at the same time PIE1 PUF1 MD0 MD1 PEN1 PE1 PPGC1 PPGC0 1 0 1 1 1 1 PIE0 PUF0 PEN0 PE0 PPG01 PCM2 PCM1 PCM0 PCS2 PCS1 PCS0 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 PRLH0 PRLL0 PRLH1 PRLL1 0 1 X Re served Reserved area Settting reload value of PPG0 H level side S...

Page 335: ...e PPG timers of both channels PPGC0 PEN0 0 and PPGC1 PEN1 0 The count operation of the PPG down counter is stopped and the output of the PPG output pin is held at a Low level When the PPG down counter of each channel underflows the reload values set in the PPG reload registers PRLL0 PRLH0 and PRLL1 PRLH1 are reloaded to the PPG down counter that underflows When an underflow occurs the underflow ge...

Page 336: ...load register PRLL0 H0 Values of 8 bits in PPG reload register PRLH0 L1 Values of 8 bits in PPG reload register PRLL1 H1 Values of 8 bits in PPG reload register PRLH1 T Count clock cycle Figure 10 5 7 shows the output waveform in the 8 8 bit PPG output operation mode Figure 10 5 7 Output Waveform in 8 8 bit PPG Output Operation Mode T L0 1 L1 1 T H0 1 H1 1 Operating start Operating stop PPG operat...

Page 337: ...independent operation mode or the 8 8 bit PPG output operation mode use a word instruction to set both High level and Low level PPG reload registers PRLL0 PRLH0 PRLL1 PRLH1 at the same Using a byte instruction may cause an unexpected pulse to be generated Example of rewriting PPG reload registers using byte instruction If you update the value in the High level PPG reload register PRLH after updati...

Page 338: ...then transferred to the PPG0 reload register PPLL0 PRLH0 Therefore when setting the reload value in the PPG1 reload registers PRLL1 PRLH1 it is necessary to set the reload value in the PPG0 reload registers PRLL0 PRLH0 simultaneously or set the reload value in the PPG0 reload registers PRLL0 PRLH0 before setting PPG1 reload value Figure 10 6 2 shows the reload timing in the 16 bit PPG output opera...

Page 339: ...erview of Delayed Interrupt Generation Module 11 2 Block Diagram of Delayed Interrupt Generation Module 11 3 Configuration of Delayed Interrupt Generation Module 11 4 Explanation of Operation of Delayed Interrupt Generation Module 11 5 Precautions when Using Delayed Interrupt Generation Module 11 6 Program Example of Delayed Interrupt Generation Module ...

Page 340: ... cancelled by software Table 11 1 1 Overview of Delayed Interrupt Generation Module Function and Control Interrupt Factor An interrupt request is generated by setting the R0 bit in the delayed interrupt request generate cancel register to 1 DIRR R0 1 An interrupt request is cancelled by setting the R0 bit in the delayed interrupt request generate cancel register to 0 DIRR R0 0 Interrupt Number 42 ...

Page 341: ... Generation Module Interrupt request latch This latch keeps the settings delayed interrupt request generation or cancellation of the delayed interrupt request generate cancel register DIRR Delayed interrupt request generate cancel register DIRR This bit generates or cancels a delayed interrupt request Interrupt Number The interrupt number used in the delayed interrupt generation module is as follo...

Page 342: ...e This section lists registers and reset values in the delayed interrupt generation module List of Registers and Reset Values Figure 11 3 1 List of Registers and Reset Values in Delayed Interrupt Generation Module 0 15 14 bit 13 12 11 10 9 8 Delay interrupt request generation release register DIRR Undefined ...

Page 343: ...e of delay interrupt request Generation of delay interrupt request Delay interrupt request generating bit Reset value XXXXXXX0B 12 13 14 11 10 9 8 15 Reset value Read Write R W Unused bit8 R W Table 11 3 1 Functions of Delayed Interrupt Request Generate Cancel Register DIRR bit name Function bit8 R0 Delayed interrupt request generate bit This bit generates or cancels a delayed interrupt request Wh...

Page 344: ...pt request generate cancel register DIRR is set to 1 the interrupt request latch is set to 1 and an interrupt request is generated to the interrupt controller An interrupt request is generated to the CPU when the interrupt controller prioritizes the interrupt request over other requests When the level of an interrupt request ICR IL is higher to that of the interrupt level mask bit ILM in the proce...

Page 345: ...rupt generation module Precautions when Using Delayed Interrupt Generation Module The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate cancel register DIRR to 0 within the interrupt processing routine Unlike software interrupts interrupts in the delayed interrupt generation module are delayed ...

Page 346: ...elay interrupt factor generating Release register DIRR_R0 EQU DIRR 0 Delay interrupt request generating bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disabled MOV I ICR15 00H Interrupt level 0 storng MOV ILM 07H Setting ILM in PS to levle 7 OR CCR 40H Interrupt enabled SETB I DIRR_R0 Delay interrupt request generating LOOP MOV A 00H No limit roop MOV ...

Page 347: ...l interrupt 12 1 Overview of DTP External Interrupt 12 2 Block Diagram of DTP External Interrupt 12 3 Configuration of DTP External Interrupt 12 4 Explanation of Operation of DTP External Interrupt 12 5 Precautions when Using DTP External Interrupt 12 6 Program Example of DTP External Interrupt Function ...

Page 348: ...data transfer is performed branching to interrupt processing after the completion of data transfer for the specified number of times Table 12 1 1 shows overview DTP external interrupt Table 12 1 1 Overview of DTP External Interrupt External interrupt DTP Function Input Pin 5 pins RX INT4 to INT7 Interrupt Factor The interrupt factor is set in unit of pins using the detection level setting register...

Page 349: ...ister ENIR DTP external interrupt input detection circuit LA4 LB4 LA5 LB5 LA6 LB6 LA7 LB7 LA0 LB0 Re served EN0 EN4 EN5 EN6 EN7 ER0 ER4 ER5 ER6 ER7 DTP external interrupt factor register EIRR Interrupt request signal Interrupt request signal Level edge selector Pin Level edge selector Pin Level edge selector Pin Level edge selector Pin Level edge selector Pin INT7 INT6 INT5 INT4 RX Re served Re se...

Page 350: ...al interrupt factors DTP external interrupt factor register EIRR This register holds DTP external interrupt factors If an enable signal is input to the DTP external interrupt pin the corresponding DTP external interrupt request flag bit is set to 1 DTP external interrupt enable register ENIR This register enables or disables DTP external interrupt requests from external peripheral devices Details ...

Page 351: ...s in DTP External Interrupt Table 12 3 1 Pins of DTP External Interrupt Pin Name Pin Function Pin Settings Required for Use in DTP External Interrupt P44 RX General purpose I O port CAN reception input Set as input port in port direction register DDR P24 INT4 General purpose I O ports DTP external interrupt inputs P25 INT5 P26 INT6 P27 INT7 Note For the block diagram of the pins see CHAPTER 4 I O ...

Page 352: ...to ER4 ER0 DTP External interrupt request flag bits These bits are set to 1 when the edges or level signals set by the detection condition select bits ELVR LB LA in the detection level setting register are input to the DTP external interrupt pin or RX pin When set to 1 When the DTP external interrupt request enable bit ENIR EN is set to 1 an interrupt request is generated to the corresponding DTP ...

Page 353: ... bit name Function bit0 bit4 to bit7 EN7 to EN4 EN0 DTP external interrupt request enable bits This register enables or disables DTP external interrupt requests via the DTP external interrupt pin or RX pin When the DTP external interrupt request flag bit EIRR ER is set to 1 with the DTP external interrupt request enable bit ENIR EN containing 1 an interrupt request is generated to the correspondin...

Page 354: ...ndition select bit Table 12 3 5 Functions of Detection Level Setting Register ELVR High bit name Function bit8 to bit15 LB7 LA7 to LB4 LA4 Detection condition select bits These bits set the levels or edges of input signals from external peripheral devices that cause interrupt factors in the DTP external interrupt pins Two levels or two edges are selectable for external interrupts and two levels ar...

Page 355: ...ure to set to 0 Reserved bit Re served Re served Re served Re served Re served Re served Table 12 3 7 Functions of Detection Level Setting Register ELVR Low bit name Function bit0 to bit1 LB0 LA0 Detection condition select bits These bits set the levels or edges of input signals from external peripheral devices that cause interrupt factors in the RX pin Two levels or two edges are selectable for e...

Page 356: ...d to 0 EIRR ER 4 Set the interrupt request enable bit corresponding to the DTP external interrupt channel to be used to 1 ENIR EN When setting the registers for the DTP external interrupt the external interrupt request must be disabled in advance ENIR EN0 0 When enabling the DTP external interrupt request ENIR EN 1 the corresponding DTP external interrupt request flag bit must be cleared in advanc...

Page 357: ...errupt request signal from the DTP external interrupt is output to the interrupt controller and the EI2 OS enable bit in the interrupt control register ICR ISE is set to 0 the interrupt processing is executed When this bit is set to 1 the EI2OS is executed Notes All interrupt requests assigned to one interrupt control register have the same interrupt level IL2 to IL0 If two or more interrupt reque...

Page 358: ... reception judge Start up external interrupt Processing and clear interrupt flag Recovery from external interrupt Memory Peripheral data trnsmission Descriptor renewal Recovery from EI2 OS processing DTP processing Interrupt processing ICR ISE EI2 OS start up 0 0 0 1 ELVR EIRR ENIR ICR YY ICR XX DTP external interrupt circuit Factor CMP IL ILM CMP Interrupt processing Other request Interrupt contr...

Page 359: ... request to other requests If the level of an interrupt request ICR IL is higher than that of the interrupt level mask bit TLM in the processor status PS and the interrupt enable bit is enabled PS CCR I 1 the CPU performs interrupt processing after completion of the current instruction execution and branches to interrupt processing At interrupt processing set the corresponding DTP external interru...

Page 360: ... of one data item the descriptor is updated and the DTP external interrupt request flag bit is cleared to prepare for the next request from the DTP external interrupt pin and RX pin When the EI2OS completes transfer of all the data control branches to the interrupt processing Figure 12 4 3 Example of Interface with External Peripheral Device Input to INT4 pin DTP factor CPU internal operation Desc...

Page 361: ...r the pulse width for edge detection must be at least three machine clocks When a level causing an interrupt factor is input with level detection set in the detection level setting register the DTP external interrupt request flag bit EIRR ER in the DTP external interrupt factor register is set to 1 and the factor is held as shown in Figure 12 5 1 With the factor held in the DTP external interrupt ...

Page 362: ... Always set the DTP external interrupt request flag bit to 0 EIRR ER at interrupt processing When the level detection is set in the detection level setting register and the level that becomes the interrupt factor remains input the external interrupt request flag bit is reset immediately even when cleared EIRR ER 0 Disable the DTP external interrupt request output as needed ENIR EN 0 or cancel the ...

Page 363: ... EIRR 0 INT4 interrupt request flag bit EN0 EQU ENIR 0 INT4 interrupt request flag bit Main program CODE CSEG START Stack pointer SP already initialized MOV I DDR2 00000000B Setting DDR2 to input port AND CCR 0BFH Interrupt disabled MOV I ICR06 00H Interrupt level 0 highest CLRB I EN4 Disable INT4 at ENIR MOV I ELVRL 00000010B INT4 is rising edge selection CLRB I ER4 Interrupt request flag of INT4...

Page 364: ... pointer upper ISCS EQU 000103H EI2OS stasu register IOAL EQU 000104H I O address register lower IOAH EQU 000105H I O address register upper DCTL EQU 000106H Data counter lower DCTH EQU 000107H Data counter upper Main ptrogram CODE CSEG START Stack pointer SP already initialized MOV I DDR1 11111111B Setting output port in DDR1 MOV I DDR5 00000000B Setting input port in DDR5 AND CCR 0BFH Interrupt ...

Page 365: ...est flag User processing RETI Recovery from interrupt processing CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FF9CH Setting vector to interrupt number 24 18H DSL WARI ORG 00FFDCH Reset vector setting DSL START DB 00H Setting to single chip mode VECT ENDS END START LOOP User processing BRA LOOP ...

Page 366: ...348 CHAPTER 12 DTP external interrupt ...

Page 367: ... bit A D converter 13 1 Overview of 8 10 bit A D Converter 13 2 Block Diagram of 8 10 bit A D Converter 13 3 Configuration of 8 10 bit A D Converter 13 4 Interrupt of 8 10 bit A D Converter 13 5 Explanation of Operation of 8 10 bit A D Converter 13 6 Precautions when Using 8 10 bit A D Converter ...

Page 368: ...enerates interrupt request by storing A D conversion results in A D data register Starts EI2OS if interrupt request generated Use of the EI2OS prevents data loss even at continuous conversion Selects start trigger from software trigger internal timer output and external trigger falling edge When the machine clock operates at 16 MHz Conversion Modes of 8 10 bit A D Converter There are conversion mo...

Page 369: ...TRT Re served BUSY A D data register ADCR ANS2 MD0 ANS1 ANS0 ANE2 ANE1 ANE0 MD1 Control circuit D A converter Analog channel selector Start up selector AVR AVcc AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 TO ADTG Comparator Sample hold circuit ST0 ST1 CT1 CT0 D9 D8 S10 D5 D6 D4 D3 D2 D1 D0 D7 Decoder Interrupt requext output TO Reserved φ A D control status register ADCS φ 2 6 2 2 2 Internal data bus Int...

Page 370: ...the comparison time sampling time and resolution of A D conversion Start selector This selector selects the trigger to start A D conversion An internal timer output or external pin input can be set as the start trigger Table 13 2 1 Pins and Interrupt Request Numbers in Block Diagram Pin Name Interrupt Request Number in Block Diagram Actual Pin Name Interrupt Request Number ADTG Trigger input pin P...

Page 371: ...t voltage immediately after A D conversion is started A D conversion is performed without being affected by the fluctuation of the input voltage during A D conversion D A converter This converter generates the reference voltage which is compared with the input voltage held in the sample hold circuit Comparator This comparator compares the D A converter output voltage with input voltage held in the...

Page 372: ...ns of 8 10 bit A D Converter Function Used Pin Name Pin Function Setting Required for Use of 8 10 bit A D Converter Trigger input ADTG General purpose I O port external trigger input Set as input port in port direction register DDR Channel 0 AN0 General purpose I O ports analog inputs Set as input port in port direction register DDR Input of analog signal enabled ADER ADE7 to ADE0 11111111 B ADER ...

Page 373: ... ADCR the interrupt request flag bit in the A D control status register ADCS INT is set to 1 When an interrupt request is enabled ADCS INTE 1 an interrupt is generated 15 14 13 12 11 10 9 8 A D data register lower ADCR L 7 6 bit 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 Analog input enable register ADER bit 0 0 0 0 0 A D control status register lower ADCS L 0 0 0 7 6 bit 5 4 3 2 1 0 1 0 A D data...

Page 374: ...tware start up bit bit9 Reserved 0 Be sure to set to 0 Reserved bit Reset value Read Write R W STS1 0 0 1 1 Software stra up Software stra up or external trigger start up Software stra up or internal timer start up Software stra up external trigger or internal timer start up A D conversion start up trigger select bit bit11 0 1 PAUS A D conversion operation doesn t stop temporarily A D conversion o...

Page 375: ...use flag bit This bit indicates the A D conversion operating state when the EI2OS function is used The PAUS bit is enabled only when the EI2OS function is used A D conversion pauses while the A D conversion results are transferred from the A D data register ADCR to memory When A D conversion pauses the PAUS bit is set to 1 After transfer of the A D conversion results to memory the 8 10 bit A D con...

Page 376: ...en set to 0 Forcibly terminates 8 10 bit A D converter When the bit is set to 1 No effect Read 1 is read when the 8 10 bit A D converter is operating and 0 is read when the 8 10 bit A D converter is stopped Note Do not perform forcible termination BUSY 0 and software start STRT 1 of the 8 10 bit A D converter simultaneously Table 13 3 2 Function of Each Bit of A D Control Status Register High ADCS...

Page 377: ...R W R W R W R W R W R W R W R W ANE1 0 0 1 1 0 0 1 1 bit1 ANE0 0 1 0 1 0 1 0 1 bit0 0 0 0 0 1 1 1 1 A D conversion start channel select bit bit5 0 0 1 1 0 0 1 1 bit4 0 1 0 1 0 1 0 1 bit3 MD1 0 0 1 1 bit7 MD0 0 1 0 1 bit6 Single conversion mode 1 enable to restart up during operation Single conversion mode 2 disable to restart up during operation Sequential conversion mode disable to restart up dur...

Page 378: ...lect bits These bits set the channel at which A D conversion start At read the channel number under A D conversion or A D converted immediately before A D conversion pauses can be checked And before A D conversion starts the previous conversion channel will be read even if these bits have already been set to the new value These bits are initialized to 000B at reset Start channel end channel A D co...

Page 379: ...t channel To terminate A D conversion forcibly write 0 to the A D conversion on flag bit in the A D control status register ADCS BUSY This mode cannot be restarted during A D conversion Pause conversion mode A D conversion for the start channel ADCS ANS2 to ANS0 starts The A D conversion pauses at termination of A D conversion for a channel When the start trigger is input while A D conversion paus...

Page 380: ...1 The parenthesized values are provided when the machine clock CT1 0 0 1 1 44 φ 5 5 µs 1 66 φ 4 12 µs 2 88 φ 5 5 µs 2 176 φ 11 0 µs 2 Compare time select bit bit12 0 0 1 1 ST1 0 1 0 1 ST0 20 φ 2 5 µs 1 32 φ 2 0 µs 2 48 φ 3 0 µs 2 128 φ 8 0 µs 2 Sampling time select bit bit14 bit13 S10 0 1 10 bits D9 to D0 8 bits D7 to D0 Resolution select bit bit15 R R 3 3 W W W W W CT0 0 1 0 1 bit11 Undefined Res...

Page 381: ...se bits set the time required from when A D conversion starts until the input analog voltage is sampled and held by the sample hold circuit Note The setting of ST1 and ST0 00B is based on operation at 8 MHz Setting based on operation at 16 MHz does not assure normal operation When these bits are read 00B is read bit15 S10 Resolution select bit This bit selects the A D conversion resolution When se...

Page 382: ... D9 bit9 6 5 4 3 2 1 0 Reset value XXXXXXXXB R Read only X Undefined Table 13 3 5 Functions of A D Data Register Low ADCR L bit name Function bit0 to bit9 D9 to D0 A D conversion data bits These bits store the A D conversion results When resolution set in 10 bits S10 0 Conversion data is stored in the 10 bits from D9 to D0 When resolution set in 8 bits Conversion data is stored in the 8 bits from ...

Page 383: ... 7 ANE1 0 1 Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input disabled Analog inpug enabled Analog input enable bit 1 AN1 bit1 ANE2 0 1 Analog input enable bit 2 AN2 Analog input ...

Page 384: ...tes The analog input pins serve as a general purpose I O port of the port 5 To use the pin as an analog input pin set the port 5 direction register DDR5 and analog input enable register ADER to switch it to an analog input pin When using the pin as an analog input pin write 0 to the bit in the port 5 direction register DDR5 corresponding to the pin to be used and turn off the output transistor Als...

Page 385: ... bit is set to 0 ADCS INT 1 with an interrupt request output enabled ADCS INTE 1 an interrupt request is generated 8 10 bit A D Converter Interrupt and EI2OS EI2OS Function of 8 10 bit A D Converter In the 8 10 bit A D converter the EI2 OS function can be used to transfer the A D conversion results from the A D data register ADCR to memory If the EI2 OS function is used the A D converted data prot...

Page 386: ...arted during A D conversion Continuous Conversion Mode ADCS MD1 MD0 10B When the start trigger is input the analog inputs from the start channel ADCS ANS2 to ANS0 to the end channel ADCS ANE2 to ANE0 are A D converted continuously When A D conversion for the end channel is terminated it is continued after returning to the analog input for the start channel To terminate A D conversion forcibly writ...

Page 387: ...ops at the termination of the A D conversion for the channel set by the A D conversion end channel select bits ANE2 to ANE0 To terminate A D conversion forcibly write 0 to the A D conversion on flag bit in the A D control status register ADCS BUSY When the A D conversion mode select bits MD1 MD0 are set to 00B this mode can be restarted during A D conversion If the bits are set to 01B this mode ca...

Page 388: ... single shot conversion mode Table 13 5 1 Conversion Order in Single shot Conversion Mode Start Channel End Channel Conversion Order in Single shot Conversion Mode AN0 pin ADCS ANS 000B AN3 pin ADCS ANE 011B AN0 AN1 AN2 AN3 End AN6 pin ADCS ANS 110B AN2 pin ADCS ANE 010B AN6 AN7 AN0 AN1 AN2 End AN3 pin ADCS ANS 011B AN3 pin ADCS ANE 011B AN3 End ...

Page 389: ...end channel select bits ANE2 to ANE0 When A D conversion for the channel set by the A D conversion end channel select bits ANE2 to ANE0 is terminated it is continued after returning to the channel set by the A D conversion start channel select bits ANS2 to ANS0 To terminate A D conversion forcibly write 0 to the A D conversion on flag bit in the A D control status register ADCS BUSY This mode cann...

Page 390: ...us conversion mode Table 13 5 2 Conversion Order in Continuous Conversion Mode Start Channel End Channel Conversion Order in Continuous Conversion Mode AN0 pin ADCS ANS 000B AN3 pin ADCS ANE 011B AN0 AN1 AN2 AN3 AN0 Repeat AN6 pin ADCS ANS 110B AN2 pin ADCS ANE 010B AN6 AN7 AN0 AN1 AN2 AN6 Repeat AN3 pin ADCS ANS 011B AN3 pin ADCS ANE 011B AN3 AN3 Repeat ...

Page 391: ...nversion pauses A D conversion for the next channel is performed The A D conversion pauses at the termination of the A D conversion for the channel set by the A D conversion end channel select bits ANE2 to ANE0 When the start trigger is input while A D conversion pauses A D conversion is continued after returning to the channel set by the A D conversion start channel select bits ANS2 to ANS0 To re...

Page 392: ...ives an example of the conversion order in the pause conversion mode Table 13 5 3 Conversion Order in Pause conversion Mode Start Channel End Channel Conversion Order in Single shot Conversion Mode AN0 pin ADCS ANS 000B AN3 pin ADCS ANE 011B AN0 Stop Start AN1 Stop Start AN2 Stop Start AN3 Stop Start AN0 Repeat AN6 pin ADCS ANS 110B AN2 pin ADCS ANE 010B AN6 Stop Start AN7 Stop Start AN0 Stop Star...

Page 393: ...iple data to memory without the loss of converted data even if A D conversion is performed continuously The conversion flow when the EI2OS is used is shown in Figure 13 5 4 Figure 13 5 4 Flow of Conversion when Using EI2OS A D converter start up Sample hold A D conversion start A D conversion finish Interrupt generating EI2 OS start up Conversion result transmission Interrupt processing Interrupt ...

Page 394: ...D conversion results are stored in the A D data register ADCR after the analog input is A D converted the interrupt request flag bit in the A D control status register ADCS INT is set to 1 A D conversion pauses for data protection while the interrupt request flag bit in the A D control status register ADCS INT is set When the INT bit is set with an interrupt request from the A D control status reg...

Page 395: ... conversion data protection function when EI2OS used EI2OS setting A D sequential conversion start up One time conversion finish Store in A D data register Two time conversion finish EI2 OS start up Note The operation flow of when the A D converter is stopped is omitted Store in A D data register Third conversion All conversion finish Finish EI2OS finish A D temporal stop EI2OS start up EI2OS star...

Page 396: ...ction is used to transfer the A D conversion results to memory do not disable output of an interrupt request If output of an interrupt request is disabled during a pause of A D conversion ADCS INTE 0 A D conversion may be restarted to rewrite data being transferred When the EI2OS function is used to transfer the A D conversion results to memory do not restart Restarting during a pause of A D conve...

Page 397: ...n using the pin as an analog input pin always set the pin to analog input enable Precaution when starting by internal timer or external trigger The input value at which the 8 10 bit A D converter is started by the internal timer output or external trigger should be set to inactive High for external trigger Holding the input value for the start trigger active may cause the 8 10 bit A D converter to...

Page 398: ...380 CHAPTER 13 8 10 bit A D converter ...

Page 399: ...ins the functions and operation of the UART0 14 1 Overview of UART0 14 2 Block Diagram of UART0 14 3 Configuration of UART0 14 4 Interrupt of UART0 14 5 UART0 baud rate 14 6 Explanation of Operation of UART0 14 7 Precautions when using UART0 ...

Page 400: ...l duplicate double buffer Transfer mode Synchronous to clock without start bit stop bit and parity bit Asynchronous start stop synchronization to clock Baud rate Special purpose baud rate generator selectable 10 types Any baud rate can be set by external clock A clock supplied from the internal clock 16 bit reload timer 0 can be used Data length 7 bits for asynchronous normal mode only 8 bits Sign...

Page 401: ...arity No Parity 0 Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits 2 1 Multiprocessor mode 8 1 1 Asynchronous 2 Clock synchronous mode 8 Clock synchronous None Setting disabled 1 1 is the address data select bit SCR A D used for controlling communications 2 During reception only one bit can be detected as the stop bit ...

Page 402: ...gister Pin Pin Pin PEN P SBL CL A D REC RXE 16 bit reload timer Start bit detection circuit Reception control cirsuit Reception bit counter Shift register for reception Reception parity counter Serial input data register Reception complete Transmission start circuit Transmission control circuit Transmission bit counter Shift register for transmission Transmission parity counter Serial outpu data r...

Page 403: ...d of the transmit bit counter transmit start circuit and transmit parity counter The transmit bit counter counts the data to transmit and outputs a transmission interrupt request when the transmission of one frame of data is completed The transmit start circuit starts transmission when serial output data register SODR is written to The transmit parity counter generates the parity bit of the data t...

Page 404: ...ter Serial output data register 0 SODR0 The register sets the transmit data Data written to this register is serial converted and then output Communication Prescaler Control Register CDCR0 The control register sets the baud rate of the baud rate generator It sets the start stop of the communication prescaler and the division rate of machine clock Serial edge select register SES0 The register is an...

Page 405: ...unction Setting Necessary for Use in UART0 SOT0 General purpose I O port Address latch enable output serial data output Set to output enable SMR0 SOE 1 SCK0 General purpose I O port read strobe output serial clock output input In clock input set pin as input port in port direction register DDR In clock output set to output enable SMR0 SCKE 1 SIN0 General purpose I O port Write strobe output pin fo...

Page 406: ...ts have been enabled SSR0 RIE 1 a reception interrupt request is generated Transmission Interrupt The transmit data empty flag bit SSR0 TDRE in the serial status register is set to 1 when data to transmit is transferred from the serial output data register SODR0 to the transmission shift register Interrupt requests are generated while transmission interrupts are enabled SSR0 TIE 1 7 6 5 4 3 2 1 0 ...

Page 407: ...perating enable bit Reset value 00000100B 12 13 11 10 9 8 bit8 R W R W W R W R W R W R W R W 14 15 RXE 0 1 Reception operating disabled Reception operating enabled Reception operating enable bit bit9 REC 0 1 Clear FRE ORE and PE flag No effection Reception error flag clear bit Read Write R W Write only Reset value W bit10 A D 0 1 Data frame Address frame Address data select bit bit11 CL 0 1 7 bits...

Page 408: ...erial status register to 0 When the bit is set to 0 The FRE ORE and PE flags are cleared When the bit is set to 1 No effect Read 1 is always read Note If reception interrupts have been enabled SSR0 RIE 1 set the REC bit to 0 only when any of the FRE ORE and PE flags contains 1 bit11 A D Address data select bit In operation mode 1 set the data format of frames to be transmitted received When the bi...

Page 409: ...chronous mode Setting disabled Operating mode select bit Operating mode SOE 0 1 General purpose I O port Output of UART0 serial data Serial data output enable bit SOT0 pin bit0 SCKE 0 1 0 Clock I O pin of general purpose I O port or UART0 Serial clock I O pin of UART0 Serial clock I O enable bit SCK0 pin bit1 Reserved Be sure to set to 0 Reserved bit bit2 bit5 bit4 bit3 CS2 CS1 CS0 Baud rate by de...

Page 410: ...rnal clock SMR0 CS2 to CS0 111B When using the pin as the serial clock output set the clock input source select bits to anything other than the external clock SMR0 CS2 to CS0 other than 111B bit2 Reserved reserved bit Always set this bit to 0 bit3 to bit5 CS2 to CS0 Clock input source select bits Set the clock input source for the baud rate Select the external clock SCK1 pin internal timer 16 bit ...

Page 411: ...disabled Reception interrupt enabled Reception interrupt enable bit bit9 Undefined Reset value X Read Write R W Unused Read only R TDRE 0 1 With transmission data writing of transmission data disabled Without transmission data writing of transmission data enabled Transmission data writing flag bit bit11 RDRF 0 1 Without reception data With reception data Reception data load flag bit bit12 FRE 0 1 ...

Page 412: ... flag bit SSR0 RDRF is set to 1 The bit is cleared to 0 when data is read from serial input register 0 SIDR0 When reception interrupts have been enabled SSR0 RIE 1 a reception interrupt request is generated if received data is loaded into the serial input data register SIDR0 bit13 FRE flaming error flag bit Detect a framing error in receive data This bit is set to 1 when a framing error occurs The...

Page 413: ... in serial input data register 0 SIDR0 When the data length is 7 bits the upper one bit SIDR1 D7 becomes invalid When received data is stored in serial input data register 0 SIDR0 the receive data load flag bit SSR0 RDRF is set to 1 When reception interrupts have been enabled SSR0 RIE 1 a reception interrupt request is generated Serial input data register 0 SIDR0 should be read with the receive da...

Page 414: ...al output data register 0 SODR0 The transmit data write flag is set to 1 at completion of data transfer to the transmit shift register The next data to transmit can be written when the transmit data write flag SSR0 TDRE contains 1 Transmission interrupts occur while enabled SSR0 TIE 1 The succeeding transmit bit data should be written with the transmit data write flag SODR TDRE containing 1 W W W ...

Page 415: ... R W Unused 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 MD 0 1 Communication prescaler operating stop Communication prescaler operating enabled Communication prescaler control bit bit7 R W R W R W R W R W 1 1 Table 14 3 5 Functions of Communication Prescaler Control Register bit name Function bit0 to bit3 DIV3 to DIV0 Communication prescaler division ratio bits These bits set the m...

Page 416: ... output too serial edge select register 0 SES0 Figure 14 3 8 serial edge select register 0 SES0 Reset value XXXXXXX0B 12 13 14 11 10 9 8 15 Reset value Read Write R W Unused NT 0 1 Normal Convert shift clock signal Clock inversion bit bit8 R W Table 14 3 6 Functions of serial edge select register 0 SES0 bit name Function bit8 NT Clock reverse bit The bit inverts the clock signal input to the UART0...

Page 417: ...f UART0 The UART0 interrupt control bits and interrupt factors are shown in Table 14 4 1 Table 14 4 1 UART0 Interrupt Control Bit and Interrupt Factor Trans missio n Recep tion Interrupt request flag bit Operating mode Interrupt Factor Interrupt factor enable bit Clear of the Interrupt request Flag 0 1 2 Recepti on SSR0 RDRF Receive data loaded into serial input data register 0 SIDR0 SSR0 RIE Read...

Page 418: ...register If the transmission interrupt enable bit SSR0 TIE contains 1 a transmission interrupt request is generated Interrupt Related to UART0 and EI2OS EI2OS Function of UART0 The UART0 supports EI2 OS Consequently EI2 OS can be started separately for receive interrupts and transmit interrupts At reception MB90895 series cannot use interrupt vectors as it contains no I2 C interface At transmissio...

Page 419: ... load flag SSR0 RDRF is set as well In each operation mode the received data in the serial input data register 0 SIDR0 is invalid if either error flag is set Operation mode 0 Asynchronous normal mode The receive data load flag bit SSR0 RDRF is set upon detection of the stop bit When a reception occurs the error flag SSR0 ORE is set Operating mode 1 asynchronous multiprocessor mode The receive data...

Page 420: ... RDRF parity error flag SSR0 PE and overrun error flag SSR0 ORE and framing error flag SSR0 FRE is set reception interrupt is requested Reception data operating mode 1 SSR0 PE ORE FRE Reception interrupt generating Reception data operating mode 0 SSR0 RDRF D0 D1 D6 D7 A D SP ST D0 D1 SP ST PE flag is disabled to detect in mode 1 PE and FRE flag are disabled to detect in mode 2 ST Start bit SP Stop...

Page 421: ...g it ready to write the next data to transmit The transmit data write flag bit SSR0 TDRE is cleared to 0 when the next data to transmit is written to serial output data register 0 SODR0 Transmission and timing of flag set are shown in Figure 14 4 2 Figure 14 4 2 Transmission and Timing of Flag Set ST Start bit D0 to D7 Data bit SP Stop bit A D Address data select bit D2 D3 D5 D6 D4 ST D0 D1 ST D0 ...

Page 422: ...bled SSR0 TIE 1 Note If the transmission in progress is disabled SCR0 TXE 1 and reception is also disabled with RXE 0 in operation mode 1 the transmit data write flag bit is set SSR0 TDRF 1 the transmission shift register stops shifting then the UART0 is disabled That transmit data is transmitted which is already written to serial output data register 0 SODR0 before transmission stops SODR ...

Page 423: ...rom 16 bit reload timer 0 as the clock input set the CS2 to CS0 bits in the serial mode register to 110B The baud rate is the value resulting from dividing the frequency of the clock signal supplied from 16 bit reload timer 0 by 2 in the clock synchronous mode or the value resulting from dividing the frequency of the supplied clock signal by 32 in the clock asynchronous mode Any baud rate can be s...

Page 424: ...aler CDCR0 MD0 DIV3 to DIV0 SMR0 CS2 to CS0 Clock input source select bit TMCSR0 CSL1 CSL0 UF SCK0 1 1 Clock sync 1 16 Asynchronous 1 2 Clock sync 1 32 Asynchronous Clock selector Down counter prescaler Baud rate CS2 to CS0 110B CS2 to CS0 111B CS2 to CS0 000B to 100B 16 bit reload timer 0 SMR0 MD1 MD0 operating select mode External clock Internal timer Dedicated baud rate generator φ 21 φ φ φ 23 ...

Page 425: ...communication prescaler is the same for the clock synchronous and asynchronous modes The division ratio at which the baud rate is determined is different for the clock synchronous and asynchronous modes Figure 14 5 2 shows the baud rate selector based on the dedicated baud rate generator Figure 14 5 2 Baud Rate Selector Based on Dedicated Baud Rate Generator Calculation expression for baud rate Ba...

Page 426: ...ased on Communication Prescaler Machine clockφ MHz Divide ratio div Communication Prescaler Control Register CDCR0 Division result φ div MHz DIV3 DIV2 DIV1 DIV0 4 4 1 1 0 0 1 6 6 1 0 1 0 8 8 1 0 0 0 6 3 1 1 0 1 2 8 4 1 1 0 0 10 5 1 0 1 1 12 6 1 0 1 0 14 7 1 0 0 1 16 8 1 0 0 0 8 2 1 1 1 0 4 12 3 1 1 0 1 16 4 1 1 0 0 16 2 1 1 1 0 8 div Division ratio based on communication prescaler Table 14 5 2 Bau...

Page 427: ...te selection bit Baud Rate bps Calculation CS2 CS1 CS0 φ div 2MHz φ div 4MHz φ div 8MHz 0 0 0 1M 2M Reserved φ div 2 0 0 1 500K 1M 2M φ div 22 0 1 0 250K 500K 1M φ div 23 0 1 1 125K 250K 500K φ div 24 1 0 0 62 5K 125K 250K φ div 25 φ Machine clock div Division ratio based on communication prescaler ...

Page 428: ...reload timer Figure 14 5 3 shows the baud rate selector based on the internal timer If the internal timer 16 bit reload timer is selected as a clock input source SMR0 CS2 to CS0 the 16 bit reload timer output pin TOT is connected internally and does not need to be connected externally to the external clock input pin SCK0 The 16 bit reload timer output pin TOT can be used as a general purpose I O p...

Page 429: ...ynchronous baud rate Clock synchronous baud rate bps X n 1 2 φ Table 14 5 4 Baud Rate and Reload Value Baud Rate bps Reload Value Clock Asynchronous start stop synchronization Clock synchronous X 21 machine cycle 2 divided X 23 Machine clock 8 frequency division X 21 machine cycle 2 divided X 23 machine cycle 8 divided 38 400 2 47 11 19 200 5 95 23 9 600 11 2 191 47 4 800 23 5 383 95 2 400 47 11 7...

Page 430: ...er DDR To set the SCK0 pin as an external clock input pin set the serial clock I O enable bit SMR0 SCKE to 0 Set the baud rate on the basis of the external clock input from the SCK0 pin To change the baud rate the external input clock cycle must be changed as the internal frequency divide ratio is fixed Figure 14 5 4 Baud Rate Selector by External Clock Calculation expression for baud rate Asynchr...

Page 431: ...le 14 6 1 shows operation mode of UART0 Table 14 6 1 Operation Mode of UART0 Operating mode Data length Synchrono us type Length of Stop Bit No Parity With Parity 0 Normal mode 7 bits or 8 bits Asynchrono us 1 bit or 2 bits 2 1 Multiprocessor mode 8 1 1 Asynchrono us 2 Clock synchronous mode 8 Clock synchronous None Setting disabled 1 1 is the address data select bit A D used for communication con...

Page 432: ... type The UART0 can only handle the NRZ Non Return to Zero data format Start of transmission reception Transmission starts when the transmission enable bit SCR0 TXE in the serial control register is set to 1 Reception starts when the reception enable bit of the serial control register SCR0 RXE is set to 1 Stop of transmission reception Transmission starts when the transmission enable bit SCR0 TXE ...

Page 433: ...ether to use the parity bit In operation mode 1 the data length is fixed at 8 bits There is no parity bit The address data bit SMR0 A D is added as bit 9 Figure 14 6 1 shows the transmit receive data format in the asynchronous mode Figure 14 6 1 Format of Transmit Receive Data Operation Mode 0 or 1 Operating mode 0 Parity bit P Stop bit SP Start bit ST Address data bit A D Operating mode 1 D8 SP S...

Page 434: ...on detection of the start bit in received data the UART0 uses serial input data register 0 SIDR0 to receive one frame of data according to the data format set in serial control register 0 SCR0 Upon completion of receiving one frame of data the receive data load flag bit SSR0 RDRF is set to 1 To read received data check the state of the error flag in the serial status register SSR0 after receiving ...

Page 435: ... and frame errors can be detected But parity errors cannot be detected ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP Non communication period Communication period Non communication period Marc level Startbit Data Stopbit SIN 01010101B transmission RXE Reception clock Sampling clock Recognition of maicrocontroller side 01010101B reception Reception clock 8 pulse Sampling clock is buil...

Page 436: ...d The transmit receive data when the parity bit enabled are shown in Figure 14 6 4 Figure 14 6 4 Transmit Receive Data when Parity Bit Enabled Reception 1 0 1 0 1 0 1 0 1 1 0 0 1 Transmission 1 0 1 1 0 0 0 Transmission SIN0 SOT0 SOT0 Parity error generated by reception in even parity SCR0 PEN 1 P 0 Transmission in even parity SCR0 PEN 1 P 0 Transmission in odd parity SCR0 PEN 1 P 1 1 0 1 1 0 0 1 S...

Page 437: ...eived on an LSB first basis The start and stop bits are not added to the transmit receive data Figure 14 6 5 shows the data format for the clock synchronous mode Figure 14 6 5 Format of Transmit Receive Data Operation Mode 2 Transmission data writing Transmission by output of serial clock 1 0 0 1 1 0 0 1 Mark level SCK0 output TXE SOT0 LSB MSB Transmission data Reception data reading Reception by ...

Page 438: ...onous mode operation mode 2 Starting communications Communication is started when transmit data is written to serial output data register 0 SODR0 When starting communication even for reception only it is always necessary to write dummy transmit data to serial output data register 0 SODR0 Table 14 6 2 Setting of Control Register Register Name bit name Setting Transmit End output serial clock Receiv...

Page 439: ...ications Upon completion of transmitting receiving one frame of data the receive data load flag bit SSR0 RDRF is set to 1 When data is received check the overrun error flag bit SSR0 ORE to ensure that the communication has performed normally ...

Page 440: ...ation mode 0 or 2 Inter CPU connection To connect two CPUs Figure 14 6 7 Example of Bidirectional Communication Connect for UART0 CL AD RXE TXE REC PEN P SBL SCR0 SMR0 0 0 0 0 0 1 0 1 0 0 RIE TIE CS1 CS0 SCKE SOE Re served MD1 MD0 CS2 RDRFTDRE Setting transmission data Write hold reception data Read PE ORE FRE SSR0 SIDR0 SODR0 DDR port direction register bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 ...

Page 441: ... an example of transferring receive data to the transmitting end to inform the transmitting end of normal reception Figure 14 6 8 Flowchart for Bidirectional Communication Start Reception data reading and processing Setting 1 byte data to SODR0 and communication With reception data With reception data Data transmission Data transmission NO NO Operating mode setting one of 0 1 2 Transmission side S...

Page 442: ...e slave CPUs are connected to a pair of common communication lines to make up the master slave communication system The UART0 can be used only as the master CPU Figure 14 6 10 Example of Master Slave Mode Communication Connect for UART0 CL AD RXE TXE REC PEN P SBL SCR0 SMR0 0 1 0 0 1 0 0 RIE TIE CS1 CS0 SCKE SOE Re served MD1 MD0 CS2 RDRFTDRE Setting transmission data Write hold reception data Rea...

Page 443: ...on cannot be used in operation mode 1 set the parity enable bit SCR0 PEN to 0 Table 14 6 3 Select of Master Slave Communication Function Operating mode Data Parity Synchro nous type Stop Bit Master CPU Slave CPU Address transmit receive Operation mode 1 A D 1 8 bit address Not provided Asynchro nous 1 bit or 2 bits Data transmit receive A D 0 8 bit data ...

Page 444: ...allocated address each slave CPU starts communications with the master CPU Figure 14 6 11 shows the flowchart for master slave communications Figure 14 6 11 Flowchart for Master Slave Communications Start Setting 0 in A D Reception operation enabled Setting SIN pin to serial data input Setting 1 byte data selecting slave CPU to D0 D7 address data and transmitting A D 1 Communicate with slave CPU R...

Page 445: ... 0 RXE 0 Setting operation mode Set the operation mode after disabling transmission and reception SCR0 TXE 0 RXE 0 When the operation mode is changed during transmission or reception the transmitted received data is not guaranteed About clock synchronous mode UART0 operation mode 2 is set as the clock synchronous mode Transmit receive data is associated with no start and stop bits Timing of enabli...

Page 446: ...428 CHAPTER 14 UART0 ...

Page 447: ...explains the functions and operation of the UART Overview of UART1 Block Diagram of UART1 Configuration of UART1 Interrupt of UART1 UART1 Baud Rate Explanation of Operation of UART1 Precautions when Using UART1 Program Example for UART1 ...

Page 448: ...l duplicate double buffer Transfer mode Synchronous to clock without start bit stop bit and parity bit Asynchronous start stop synchronization to clock Baud rate Dedicated baud rate generator The baud rate can be selected from among eight types Any baud rate can be set by external clock A clock supplied from the internal clock 16 bit reload timer 0 can be used Data length 7 bits for asynchronous n...

Page 449: ...ty 0 Asynchronous mode Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits 2 1 Multiprocessor mode 8 1 1 Asynchronous 2 Synchronous mode 8 Synchronous None Setting disabled 1 1 is the address data select bit bit 11 of SCR1 register A D used for controlling communications 2 During reception only one bit can be detected as the stop bit ...

Page 450: ...erial control register 1 Pin Pin Pin BDS PEN P SBL CL A D REC RXE 16 bit reload timer Start bit detection circuit Reception control circuit Reception bit counter Shift register for reception Reception parity counter Serial input data register 1 Reception finish Transmission start circuit Transmission control circuit Transmission bit counter Shift register for transmission Transmission parity count...

Page 451: ...er on a bit by bit shift basis in accordance with the transfer rate The receive parity counter detects a parity bit in received data Transmission control circuit The transmit controller is composed of the transmit bit counter transmit start circuit and transmit parity counter The transmit bit counter counts the transmit data and outputs a transmit interrupt request when transmission of one piece o...

Page 452: ... or disables transmitting Enables or disables receiving Serial status register 1 SSR1 The status register checks the transmission reception state and error state and sets enabling disabling of the transmit receive interrupt request Serial input data register 1 SIDR1 The serial input data register retains the receive data The serial input is converted and then stored in this register Serial output ...

Page 453: ...1 UART1 Pin Pin Name Pin Function Setting Necessary for Use in UART SOT1 General purpose I O port serial data output Set to output enable SMR1 register bit 0 SOE 1 SCK1 General purpose I O port serial clock output input In clock input set pin as input port in port direction register DDR In clock output set to output enable SMR register bit 1 SCKE 1 SIN1 General purpose I O port serial data input S...

Page 454: ...curred When a receive interrupt is enabled bit 9 RIE 1 a receive interrupt request is generated to the interrupt controller Transmission Interrupt When transmit data is transferred from the serial output data register SODR1 to the transmit shift register the transmit data empty flag bit bit 11 TDRE in the serial status register SSR1 is set to 1 If a transmit interrupt is enabled bit 8 TIE 1 a tran...

Page 455: ... Transmission enable bit Reset value 00000100B 12 13 11 10 9 8 bit8 R W R W W R W R W R W R W R W 14 15 RXE 0 1 Reception disabled Reception enabled Reception enable bit bit9 REC 0 1 Clear PE ORE and FRE bit No effection Reception error flag clear bit Read write R W Write only Reset value W bit10 A D 0 1 Data frame Address frame Address data select bit bit11 CL 0 1 7 bits 8 bits Data length select...

Page 456: ...RE flags When set to 1 No effect When read 1 always read Note When a receive interrupt is enabled bit 9 RIE 1 set the bit10 REC bit to 0 only when any one of the PE ORE and FRE flags is set to 1 bit11 A D Address data select bit In operation mode 1 asynchronous multiprocessor mode set the data format of the frame to be transmitted received When bit set to 0 Data frame set When bit set to 1 Address...

Page 457: ...disabled Oerating mode select bit Operating mode SOE 0 1 General purpose I O port Serial data output of UART1 Serial data output enable bit SOT1 pin bit0 SCKE 0 1 0 1 Clock input pin of general purpose I O port or UART Serial clock output pin of UART1 Serial clock I O enable bit SCK1 pin bit1 RST UART initialization bit No effection Initialization of all register in UART1 bit2 bit5 bit4 bit3 CS2 C...

Page 458: ...ut source select bits Set the clock input source for the baud rate Select the external clock SCK1 pin internal timer 16 bit reload timer or dedicated baud rate generator as the clock input source Set the baud rate when selecting the dedicated baud rate generator bit6 bit7 MD0 MD1 Operation mode select bits Select the UART1 operation mode Note 1 In operation mode 1 asynchronous multiprocessor mode ...

Page 459: ...bled Reception interrupt generating enable bit bit9 TDRE 0 1 With transmission data transmission data writing disabled Without transmission data transmission data writing enabled Transmission data writing flag bit bit11 RDRF 0 1 Without reception data With reception data Reception data load flag bit bit12 FRE 0 1 Without framing error With framing error Framing error flag bit bit13 Without overrun...

Page 460: ...es invalid bit11 TDRE Transmit data write flag bit Show the status of the serial output data register 1 This bit is cleared to 0 when send data is written to the serial output register 1 SODR1 This bit is set to 1 when data is loaded to the send shift register and transmission starts When a transmission interrupt is enabled bit 8 TIE 1 a transmit interrupt request is issued when data written to th...

Page 461: ...is set bit 14 ORE 1 data in the serial input data register SIDR1 is invalid bit15 PE parity error flag bit Detect an overrun error in receiving This bit is set to 1 when a parity error occurs This bit is cleared when 0 is written to the receive error flag clear bit SCR1 register bit 10 REC When a receive interrupt is enabled bit 9 RIE 1 a receive interrupt request is issued when a parity error occ...

Page 462: ...1 When the data length is 7 bits the upper one bit SIDR1 D7 becomes invalid When receive data is stored in the serial input data register 1 SIDR1 the receive data load flag bit SSR1 register bit 12 RDRF is set to 1 When a receive interrupt is enabled SSR1 register bit 9 RIE 1 a receive interrupt request is issued Read SIDR1 when the receive data load flag bit SSR1 register bit 12 RDRF is set to 1 ...

Page 463: ...ta is written to SODR1 The transmit data write flag is set to 1 at completion of data transfer to the transmit shift register When the transmit data write flag SSR1 register bit 11 TDRE is 1 the transmit data can be written When a transmit interrupt is enabled SSR1 register bit 8 TIE 1 a transmit interrupt occurs The transmit bit data should be written with the transmit data write flag SCR1 regist...

Page 464: ...set value Read Write R W Unused 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MD 0 1 Communication prescaler operating stop Communication prescaler operating enabled Communication prescaler control bit bit15 Reserved 0 Be sure to set to 0 Reserved bit bit11 R W R W R W R W R W Reset value Table 15 3 5 Functions of Communication Prescaler Control Register 1 CDCR1 1 2 bit name Function bit8 to bit...

Page 465: ...control bit This bit enables or disables the communication prescaler When set to 0 Stops communication prescaler When set to 1 Operates communication prescaler Table 15 3 5 Functions of Communication Prescaler Control Register 1 CDCR1 2 2 bit name Function ...

Page 466: ...UART1 interrupt control bits and interrupt factors are shown in Table 15 4 1 UART1 Interrupt Control Bit and Interrupt Factor Trans missio n Recep tion Interrupt request flag bit Operating mode Interrupt Factor Interrupt factor enable bit Clear of the Interrupt request Flag 0 1 2 Recepti on SSR1 RDRF Receive data loaded into serial input data register 1 SIDR1 SSR1 RIE Reading receive data SSR1 ORE...

Page 467: ...e transmit shift register the transmit data write flag bit SSR1 register bit 11 TDRE is set to 1 When a transmit interrupt is enabled SSR1 register bit 8 TIE 1 a send interrupt request is issued Interrupt Related to UART1 and EI2OS EI2OS Function of UART1 The UART1 supports EI2OS Consequently EI2OS can be started separately for receive interrupts and transmit interrupts At reception EI2OS can be u...

Page 468: ...well In each operation mode the received data in the serial input data register 0 SIDR1 is invalid if either error flag is set If any of the flags is set to the each operation mode the serial input data registers 1 SIDR1 that have received are invalid Operation mode 0 Asynchronous normal mode The receive data load flag bit SSR1 register bit 12 RDRF is set when the stop bit is detected The error fl...

Page 469: ...verrun error flag SSR1 register bit 14 ORE and framing error flag SSR1 register bit 13 FRE is set reception interrupt is requested to interrupt controller Reception data operating mode 1 SSR1 PE ORE FRE Reception interrupt generating Reception data operating mode 0 SSR1 RDRF D0 D1 D6 D7 A D SP ST D0 D1 SP ST PE flag is not detected in operating mode 1 PE and FRE flag are detected in operating mode...

Page 470: ...ransmit interrupt is enabled SSR1 register bit 8 TIE 1 a send interrupt request is issued to interrupt controller when the transmit data load flag bit SSR1 register bit 11 TDRE is set ST D0 to D7 SP A D D2 D3 D5 D6 D4 ST D0 D1 ST D0 D2 D3 D1 D7 SP A D SP SODR1 writing Transmission interrupt request Transmission interrupt generating Operating mode 1 2 SSR1 TDRE SOT1 output D3 D4 D6 D7 D5 D0 D1 D2 D...

Page 471: ...internal timer When using the internal clock supplied from the 16 bit reload timer as a clock input source set the CS2 to CS0 bits in SMR1 bit 5 to 3 to 110B The baud rate is the value at which the frequency of the clock supplied from the 16 bit reload timer as it is in the clock synchronous mode and the value at which the frequency of the supplied clock is divided by 16 in the clock asynchronous ...

Page 472: ...scaler CDCR1 MD0 DIV2 to DIV0 SMR1 CS2 to CS0 Clock input source select bit TMCSR1 CSL1 CSL0 UF SCK1 1 1 Clock synchronous 1 16 Asynchronous 1 1 Clock synchronous 1 16 Asynchronous Clock selector Down counter prescaler Baud rate CS2 to CS0 110B CS2 to CS0 111B CS2 to CS0 000B to 101B 16 bit reload timer 1 SMR1 MD1 MD0 Operating mode select bit External clock Internal timer Dedicated baud rate gene...

Page 473: ...ommunication prescaler is the same for the clock in synchronous and asynchronous modes The division ratio at which the baud rate is determined is different for the clock in synchronous and asynchronous mode shows the baud rate selector based on the dedicated baud rate generator Figure 15 5 2 Baud Rate Selector Based on Dedicated Baud Rate Generator Calculation expression for baud rate Baud rate in...

Page 474: ...Table 15 5 1 Division Ratio Based on Communication Prescaler MD DIV2 DIV1 DIV0 div 0 Stops 1 0 0 0 1 frequency division 1 0 0 1 2 frequency division 1 0 1 0 3 frequency division 1 0 1 1 4 frequency division 1 1 0 0 5 frequency division 1 1 0 1 6 frequency division 1 1 1 0 7 frequency division 1 1 1 1 8 frequency division div Division ratio based on communication prescaler Table 15 5 2 Baud Rate As...

Page 475: ...ision ratio is set by the clock input source select bits SMR1 register bit 5 to 3 CS2 to CS0 Table 15 5 3 Baud Rate Clock Synchronous CS2 CS1 CS0 CLK Synchronous Calculation 0 0 0 2Mbps φ div 1 0 0 1 1Mbps φ div 2 0 1 0 500kbps φ div 4 0 1 1 250kbps φ div 8 1 0 0 125kbps φ div 16 1 0 1 62 5kbps φ div 32 φ Machine clock frequency div Division ratio based on communication prescaler ...

Page 476: ... a clock input source SMR1 register bit 5 to 3 CS2 to CS0 the 16 bit reload timer output pin TOT is connected internally and does not need to be connected externally to the external clock input pin SCK The 16 bit reload timer output pin TOT can be used as a general purpose I O port unless otherwise used Figure 15 5 3 Baud Rate Selector by Internal Timer 16 bit Reload Timer Output Calculation expre...

Page 477: ...rt stop synchronization Clock synchronous N 21 machine cycle divided by 2 N 23 machine cycle divided by 8 N 21 machine cycle divided by 2 N 23 machine cycle divided by 8 38 400 2 47 11 19 200 5 95 23 9 600 11 2 191 47 4 800 23 5 383 95 2 400 47 11 767 191 1 200 95 23 1 535 383 600 191 47 3 071 767 300 383 95 6 143 1 535 N Division ratio based on communication prescaler for 16 bit reload timer Sett...

Page 478: ... register DDR Set the serial dock I O enable bit SMR1 register bit 1 SCKE to 0 Set the baud rate on the basis of the external clock input from the SCK1 pin Since the internal division ratio is fixed the cycle of the external input clock must be changed when changing the baud rate Figure 15 5 4 Baud Rate Selector by External Clock Calculation expression for baud rate Asynchronous baud rate f 16 bps...

Page 479: ...r operation mode 2 as clock synchronous mode must be adopted for the two CPUs For the asynchronous mode select operation mode 1 asynchronous multiprocessor mode SMR1 register bit 7 6 MD1 MD0 00B for the synchronous mode select operation mode 2 clock synchronous mode SMR1 register bit 7 6 MD1 MD0 10B For the master slave type connection operation mode 1 asynchronous multiprocessor mode SMR1 registe...

Page 480: ...rol register SCR1 register bit 9 RXE is set to 1 Stop of transmission reception Transmission stops when the transmission enable bit of the serial control register SCR1 register bit 8 TXE is set to 0 Reception stops when the reception enable bit of the serial control register SCR1 register bit 9 RXE is set to 0 Stop during transmission reception When reception is disabled during receiving during da...

Page 481: ...se of the parity bit can be specified In operation mode 1 Asynchronous multiprocessor mode the data length is fixed to 8 bits The address data bit SCR1 register bit 11 A D is added to bit 9 shows the transmit receive data format in the asynchronous mode Figure 15 6 1 Format of Transmit Receive Data Operation Mode 0 or 1 Operating mode 0 Parity bit P Stop bit SP Start bit ST Address Data bit A D Op...

Page 482: ...ys performed When the start bit of receive data is detected the serial input data register 1 SIDR1 receives one frame of data and stores data to the serial input data register 1 SIDR1 according to the data format specified in the serial control register 1 SCR1 At completion of receiving one frame of data the receive data load flag bit SSR1 register bit 12 RDRF is set to 1 When the status of the er...

Page 483: ...al mode The parity addition enable bit SCR1 register bit 15 PEN is used to specify whether there is parity or not and the parity select bit SCR1 register bit 14 P is used to select odd or even parity There is no parity bit in operation modes 1 asynchronous multiprocessor mode ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP Non communication period Communication period Non communication...

Page 484: ...d Reception 1 0 1 0 1 0 1 0 1 1 0 0 1 Transmission 1 0 1 1 0 0 0 Transmission SIN1 SOT1 SOT1 Parity error generated with reception in even parity SCR1 PEN 1 P 0 Transmission in even parity SCR1 PEN 1 P 0 Transmission in odd parity SCR1 PEN 1 P 1 1 0 1 1 0 0 1 ST Start bit SP Stop bit Note Parity bit is not set in operating mode 1 Data ST SP ST SP ST SP Parity ...

Page 485: ... the transmit and receive bits count must be supplied When the internal clock dedicated baud rate generator or internal timer has already selected SMR1 register bit 5 to 3 CS2 to CS0 000B to 101B or 110B and data is transmitted the synchronous clock for data reception is generated automatically When the external clock has already selected SMR1 register bit 5 to 3 CS2 to CS0 111B the clock for exac...

Page 486: ...F is set to 1 When data is received check the overrun error flag bit SSR1 register bit 14 ORE to ensure that the communication has performed normally Table 15 6 2 Setting of Control Register Register Name bit name Setting Transmit End output serial clock Receive End input serial clock Serial mode register 1 SMR1 MD1 MD0 Set clock synchronous mode MD1 MD0 10B CS2 CS1 CS0 Set clock input source Dedi...

Page 487: ...ronous normal mode clock synchronous mode shown in is required Figure 15 6 6 Setting of Operation Modes 0 2 Asynchronous Normal Mode and Clock Synchronous Mode for UART1 Inter CPU connect Connect the two CPUs CL AD RXE TXE REC PEN P SBL SCR1 SMR1 0 0 0 0 0 1 0 1 0 0 RIE TIE CS1 CS0 SCKE SOE Re served MD1 MD0 CS2 RDRFTDRE Setting transmission data write holding reception data read PE ORE FRE SSR1 S...

Page 488: ...g gives an example of transferring receive data to the transmitting end to inform the transmitting end of normal reception Figure 15 6 8 Flowchart for Bidirectional Communication SOT SIN SCK SOT SIN SCK CPU 1 CPU 2 Output Input Start Reading reception data and processing Setting 1 byte data to SODR and communicating With reception data With reception data Data transmission Data transmission NO NO ...

Page 489: ...tiprocessor Mode for UART1 Inter CPU connection One master CPU and two or more slave CPUs are connected to a pair of common communication lines to make up the master slave communication system The UART1 can be used only as the master CPU CL AD RXE TXE REC PEN P SBL SCR1 SMR1 0 1 0 0 1 0 0 RIE TIE CS1 CS0 SCKE SOE Re served MD1 MD0 CS2 RDRFTDRE PE ORE FRE SSR1 SIDR1 SODR1 DDR port direction registe...

Page 490: ... in operation mode 1 asynchronous multiprocessor mode set the parity add enable bit SCR1 register bit 15 PEN to 0 SOT1 SIN1 SOT SIN SOT SIN Master CPU Slave CPU 0 Slave CPU 1 Table 15 6 3 Selection of Master Slave Communication Function Operating mode Data Parity Synchro nous type Stop Bit Master CPU Slave CPU Address transmit receive Operation mode 1 A D 1 8 bit address None Asynchro nous 1 bit o...

Page 491: ... match with the allocated address each slave CPU starts communications with the master CPU shows the flowchart for master slave communications Figure 15 6 11 Flowchart for Master Slave Communications Start Setting 0 to A D Reception operating enable Slave to D0 to D7 Setting 1 byte data selecting CPU address data and transmission A D 1 Communicating with slave CPU Reception operating disabled End ...

Page 492: ... Setting operation mode Set the operation mode after disabling sending and receiving SCR1 register bit 8 TXE 0 bit 9 RXE 0 When the operation mode is changed during transmission or reception the transmitted received data is not guaranteed Clock synchronous mode Operation mode 2 clock synchronous mode is set as the clock synchronous mode Send and receive data do not have start and stop bits Timing ...

Page 493: ...ntrol register DDR1 EQU 000011H Port1 data direction register CDCR1 EQU 00001BH Communication prescaler register 1 SMR1 EQU 000024H Mode control register 1 SCR1 EQU 000025H Control register 1 SIDR1 EQU 000026H Input data register 1 SODR1 EQU 000026H Output data register 1 SSR1 EQU 000027H State register 1 REC EQU SCR1 2 Reception error flag clear bit Main program CODE CSEG ABS 0FFH START Assume st...

Page 494: ... Enable interrupt LOOP MOV A 00H No limit roop MOV A 01H BRA LOOP Interrupt program WARI MOV A SIDR1 Read reception data CLRB I REC Clear reception interrupt requestflag User processing RETI Recavery from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 0FF68H Setting vector of interrupt 37 25H DSL WARI ORG 0FFDCH Setting reset vector DSL START DB 00H Setting single chip mode VECT ENDS ...

Page 495: ...he CAN controller 16 1 Overview of CAN Controller 16 2 Block Diagram of CAN Controller 16 3 Configuration of CAN Controller 16 4 Interrupts of CAN Controller 16 5 Explanation of Operation of CAN Controller 16 6 Precautions when Using CAN Controller 16 7 Program Example of CAN Controller ...

Page 496: ...e frames receiving The baud rate ranges from 10 KBps to 1 Mbps at 16 MHz machine clock frequency The CAN controller equips eight transmit receive message buffers The standard frame format provides transmitting and receiving with 11 bit ID and the extended frame format 29 bit ID Message data can be set from 0 byte to 8 bytes Message buffer configuration can be performed at a multilevel The CAN cont...

Page 497: ... interrupt generating circuit Acceptance filter Reception buffer determine circuit Reception complemet interrupt generating circuit RAM address generating circuit Transmission DLC Reception DLC Stuff error Reception buffer Reception buffer transmissio buffer reception DLC transmission DLC ID selection Arbitration lost Arbitration check Acknowledge error check ACK error Form error Bit error check F...

Page 498: ...ch message buffer Transmit cancel register TCANR This register cancels transmit requests held in each buffer message Transmit RTR register TRTRR This register selects a frame format transmitted to each message buffer It selects the data frame or remote frame Remote frame receive waiting register RFWTR This register sets the condition for transmitting start when a transmit request of the data frame...

Page 499: ...aler The prescaler generates a bit timing clock at a frequency of 1 1 to 1 64 of the system clock It sets the operation clock TQ Bit timing generator This generator detects a bit timing clock signal to generate a sync segment and time segments 1 and 2 Node status transition interrupt generator This generates a node status transition interrupt signal when the node status transits Bus state identifi...

Page 500: ...lock Diagram for Pins of CAN Controller Table 16 3 1 CAN controller pin Pin name Function Pin setting during used by CAN TX Transmitting output pin General purpose I O port Set transmitting output pin If TOE bit of CSR register 1 RX Receiving input pin General purpose I O port Set receiving input pin If bit4 of DDR4 register 0 Reference For details of pin block diagram see section 4 ...

Page 501: ...smission cancel register TCR Transmission completion register RCR Reception completion register RRTRR Reception RTR register ROVRR Reception overrun register RIER Reception completion interrupt enable register CSR Control status register RTEC Transmission reception error counter AMSR Acceptance mask select register BTR Bit timing register AMR1 Acceptance mask select register 1 AMR0 Acceptance mask...

Page 502: ...gister 2 IDR3 ID register 3 IDR4 ID register 4 IDR5 ID register 5 IDR6 ID register 6 IDR7 ID register 7 Message buffer ID register Reset value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXX...

Page 503: ...erated after a completion of message receiving When a node status transition interrupt is enabled CSR NIE 1 the NT bit in the CAN status register is set to 1 and a node status transition interrupt request is generated after the node status transits bit15 bit7 bit0 bit8 DTR0 Data register 0 8byte DTR1 Data register 1 8byte DTR2 Data register 2 8byte DTR3 Data register 3 8byte DTR4 Data register 4 8...

Page 504: ...tus register CSR Only in the case of HALT bits unchanged use any bits operation instructions without problems initialization of the macro instructions e t c Reset value 0 0 X X X 0 0 0 B 12 13 11 10 9 15 14 8 R R R W R RS Reception status bit Not receiving message In receiving message bit14 0 1 TS Transmission status bit Not transmitting message In transmitting message bit15 0 1 Node status bit NS...

Page 505: ... those for the NS1 and NS2 bits When set to 0 The bit is cleared When set to 1 Disables bit setting Read using read modify write instructions 1 always read bit11 to bit13 Unused bits Read The value is undefined Write No effect bit14 RS Receive status bit This bit indicates whether the message is being received Message being received Bit set to 1 For example if the message is on the bus even during...

Page 506: ... register CSR Only in the case of HALT bits unchanged use any bits operation instructions without problems initialization of the macro instructions e t c Reset value 0 X X X X 0 0 1 B 4 5 3 2 1 7 6 0 R W W R W R W bit7 bit1 Unused X Undefined W Write only R W Read Write Reset value Be sure to set this bit to 0 NIE 0 1 Node status transition interrupt output enable bit Node status transition interr...

Page 507: ...ring Note To check whether the bus is halted read the value of the HALT bit Before switching to the low power consumption mode write 1 to the HALT bit and then read the HALT bit to check that the bus is completely halted CSR HALT 1 Conditions for canceling bus halt The state in which the bus is halted by a hardware reset or by writing 1 to the HALT bit is cancelled after 0 is written to the HALT b...

Page 508: ...s interrupt generation When set to 1 Enables interrupt generation bit3 to bit6 Unused bits Read The value is undefined Write No effect bit7 TOE Transmit output enable bit This bit switches between general purpose I O port and transmit pin TX When set to 0 Functions as general purpose I O port When set to 1 Functions as transmit pin TX Table 16 3 3 Functions of Control Status Register Low CSR L 2 2...

Page 509: ... 0 0 X X 0 0 0 B 4 5 3 2 1 bit7 6 0 R W R W R W R W R W bit5 bit2 bit6 bit7 R W Unused X Undefined R W Read Write Reset value MBP1 1 0 0 0 1 MBP0 Message buffer pointer bit 1 1 0 Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 1 0 0 0 1 1 1 0 0 MBP2 0 0 0 1 1 1 1 Message buffer 4 Message buffer 5 Message buffer 6 message buffer 7 RCE 0 1 Last event Reception complete bit No rec...

Page 510: ... 1 always read bit6 TCE last event transmit ting completed bit This bit indicates that the transmitting the last event is completed Transmitting of last event completed Sets bit to 1 when TCx bit in transmission complete register set TCR TCx 1 Nothing is related to the setting of the reception complete interrupt enable register TIER The number x of the message buffer that completes receiving the m...

Page 511: ...1 REC0 6 R 5 R 4 R 3 R 2 R 1 R 0 R Table 16 3 5 Functions of Receive Transmit Error Counter RTEC bit name Function bit0 to bit7 REC7 to 0 Receive error counter bits Reception error counter value 96 or more The node status changes to warning CSR NS1 NS0 01B Reception error counter value 128 or more The node status changes to error passive CSR NS1 NS0 10B Reception error counter value 256 or more St...

Page 512: ...REC Reception error counter TEC Transmission error counter REC 128 and TEC 128 REC 96 or TEC 96 REC 128 or TEC 128 Bus off HALT 1 Warning error active After 0 was written to the HALT bit of the control status register CSR continuous 11 bit High levels recessive are input 128 times to the receive input pin RX to transit Table 16 3 6 Node Status Node Status State of CAN Bus Error active Normal state...

Page 513: ...ivide the frequency of the system clock to determine the time quantum TQ of the CAN controller bit6 bit7 RSJ1 to 0 resynchronous jump width setting bits 1 0 These bits set the resynchronous jump width RSJW bit8 to bit11 TS1 3 to 1 0 time segment 1 setting bits 3 to 0 These bits set the time of time segment 1 TSEG1 Time segment 1 is equivalent to propagation segment PROP_EG and phase buffer segment...

Page 514: ...hysical delay among networks is adjusted PHASE_SEG phase segment The phase shift due to oscillation errors is adjusted Bit time segments of Fujitsu CAN controller The propagation segment PROP_SEG and phase segment 1 PHASE_SEG1 are used as a single segment of time segment 1 TSEG1 The phase segment 2 PHASE_SEG2 is used as the time segment 2 TSEG2 Figure 16 3 11 Bit Time Segments of CAN Controller TS...

Page 515: ...ent SYNC_SEG time segment 1 2 TSEG1 TSEG2 re synchronous jump width RSJW frequency divided PSC Figure 16 3 12 Calculation of Bit Timing TQ PSC 1 CLK BT SYNC_SEG TSEG1 TSEG2 1 TS1 1 TS2 1 TQ 3 TS1 TS2 TQ RSJW RSJ 1 TQ For each segment the following conditions shoud be met When PSC is 1 to 63 2 to 64 devided clock TSEG1 2TQ TSEG1 RSJW TSEG2 2TQ TSEG2 RSJW When PSC is 0 1 devided clock TSEG1 5TQ TSEG...

Page 516: ...ump width when resynchronous jump width is 4TQ Unit TQ Unit us RSJ 1 Division of TQ RSJW RSJ 1 TQ 1 0 5 2 1 3 1 5 4 2 5 Condition of TSEG2 Unit TQ Unit TQ Unit us RSJW RSJ 1 TQ TSEG2 RSJW TSEG2 RSJW 1 1 0 5 2 2 1 3 3 1 5 4 4 2 6 Condition of TSEG1 TSEG1 Delay time RSJW Assuming that delaytime is 50ns 2 4TQ 5TQ TSEG1 5 Unit TQ 2 Calculation of bit time BT based or the above setting and condition BT...

Page 517: ...bled message buffer 1 enable Message buffer enable bit 1 bit1 BVAL2 0 1 message buffer 2 disabled message buffer 2 enable Message buffer enable bit 2 Read Write R W Reset value bit2 BVAL3 0 1 message buffer 3 disabled message buffer 3 enable Message buffer enable bit 3 bit3 BVAL4 0 1 message buffer 4 disabled message buffer 4 enable message buffer 5 disabled message buffer 5 enable Message buffer ...

Page 518: ...1 A message can be transmitted and received to and from the message buffer x When Message buffer set disabled BVALx 0 During transmitting Transmitting and receiving are disabled after message transmitting is completed or a transmit error is terminated During receiving Transmitting and receiving are disabled immediately When the received message is stored in the mes sage buffer transmitting and rec...

Page 519: ...buffer 1 Standard format ID11bit are used Extended format ID29bit are used ID Format select bit 2 message buffer 2 Standard format ID11bit are used Extended format ID29bit are used ID Format select bit 3 message buffer 3 Standard format ID11bit are used Extended format ID29bit are used ID Format select bit 4 message buffer 4 Standard format ID11bit are used Extended format ID29bit are used ID Form...

Page 520: ... used in the message buffer x When set to 0 Uses message buffer x in standard format ID11 bits When set to 1 Uses message buffer x in extended format ID29 bits Note The IDE register IDER should be set after having the message buffer x disabled BVALR BVALx 0 Setting the IDE register IDER with the message buffer x being enabled may store message unnecessary received ...

Page 521: ...ransmit request Transmission request bit 2 message buffer 2 Read Write R W Reset value bit2 TREQ3 0 1 Not request transmission When reception no request transmission Transmit repuest When reception transmit request Transmission request bit 3 message buffer 3 bit3 TREQ4 0 1 Not request transmission When reception no request transmission Transmit repuest When reception transmit request Not request t...

Page 522: ...sage buffer x that accepts the transmit request These bits remain 1s during the transmit being requested These bits are cleared to 0 when transmitting is completed or the transfer request is cancelled Clearing a transmit request when transmitting is completed TREQx 0 overrides setting of the transmit request bit when 0 is written TREQx 1 if both occur at the same time Read using read modify write ...

Page 523: ...mote frame Remote frame setting bit 2 message buffer 2 Transmit a data frame Transmit a remote frame Remote frame setting bit 3 message buffer 3 Transmit a data frame Transmit a remote frame Remote frame setting bit 4 message buffer 4 Transmit a data frame Transmit a remote frame Remote frame setting bit 5 message buffer 5 Transmit a data frame Transmit a remote frame Remote frame setting bit 6 me...

Page 524: ... to each bit the remote frame format is set Table 16 3 11 Functions of Transmission RTR Register TRTRR Bit name Function bit0 to bit7 TRTR7 to 0 Remote frame setting bits 7 to 0 These bits set the transfer format of the message buffer x for transmitting or receiving When set to 0 Sets data frame format When set to 1 Sets remote frame format ...

Page 525: ...Transmitting after remote frame received Remote frame receiving wait bit 2 message buffer 2 transmission immediately Transmitting after remote frame received Remote frame receiving wait bit 3 message buffer 3 transmission immediately Transmitting after remote frame received Remote frame receiving wait bit 4 message buffer 4 transmission immediately Transmitting after remote frame received Remote f...

Page 526: ...rame set Transmitting is started immediately even if the receive RTR register is already set in the message buffer x RRTRR RRTRx 1 When set to 1 Starts transmitting after remote frame is received in message buffer x in which a request to transmit a data frame Note When transmitting a remote frame do not write 1 to the RFWTx bit Reference For details on the transmission request register TREQR see 1...

Page 527: ...t 1 bit1 TCAN2 0 1 No effect on operation Cancel transmission request for message buffer 2 Transmission on cancel bit 2 Write only W Reset value bit2 TCAN3 0 1 No effect on operation Cancel transmission request for message buffer 3 Transmission on cancel bit 3 bit3 TCAN4 0 1 No effect on operation Cancel transmission request for message buffer 4 No effect on operation Cancel transmission request f...

Page 528: ...essage buffer x in the transmit wait state When set to 0 No effect on operation When set to 1 Cancels transmission request for message buffer x When a transmission request is cancelled by setting 1 to the TCANx bit the TREQx bit corresponding to the message buffer x is cleared TREQx 0 for which transmission request is cancelled Read 0 is always read Note The transmission cancel register TCANR is a...

Page 529: ...te Transmission complete bit 1 message buffer 1 bit1 TC2 0 1 Not Transmitting complete Not transmission Transmitting complete Transmission complete bit 2 message buffer 2 Read Write R W Reset value bit2 TC3 0 1 Not Transmitting complete Not transmission Transmitting complete Transmission complete bit 3 message buffer 3 bit3 TC4 0 1 Not Transmitting complete Not transmission Transmitting complete N...

Page 530: ...0 Clears bits if transmitting already completed When set to 1 No effect Read using read modify write instructions 1 always read Setting the TCx bit when transmitting is completed TCx 1 overrides clearing of the TCx bit when 0 is written TCx 0 if both occur at the same time When the TREQx bit in the transmit request register TREQR is set TREQR TREQx 1 the TCx bit is cleared TCx 0 Generation of tran...

Page 531: ...te interrupt enable Transmission interrupt enable bit 2 message buffer 2 Transmission complete interrupt disabled Transmission complete interrupt enable Transmission interrupt enable bit 3 message buffer 3 Transmission complete interrupt disabled Transmission complete interrupt enable Transmission interrupt enable bit 4 message buffer 4 Transmission complete interrupt disabled Transmission complet...

Page 532: ...ame Function bit0 to bit7 TIE7 to 0 Transmission complete interrupt enable bits 7 to 0 These bits enable or disable a transmission complete interrupt for the message buffer x When set to 0 Disables transmit complete interrupt for message buffer x When set to 1 Enables transmit complete interrupt for message buffer x ...

Page 533: ...complete bit1 RC2 0 1 Not reception complete Not receiving Reception complete Reception complete bits2 message buffer 2 Read Write R W Reset value bit2 RC3 0 1 Not reception complete Not receiving Reception complete Reception complete bits3 message buffer 3 bit3 RC4 0 1 Not reception complete Not receiving Reception complete Not reception complete Not receiving Reception complete Reception complet...

Page 534: ...to 0 Clears bits when receiving already completed When set to 1 No effect Read using read modify write instructions 1 always read Setting the RCx bit when receiving is completed TCx 1 overrides clearing of the RCx bit when 0 is written RCx 0 if both occur at the same time Generation of reception complete interrupt If the transmit complete enable register is set RIER RIEx 1 a reception complete int...

Page 535: ... frame received Not remote frame received Remote frame received Remot frame receive bits3 message buffers 3 Not remote frame received Remote frame received Remot frame receive bits4 message buffers 4 Not remote frame received Remote frame received Remot frame receive bits5 message buffers 5 Not remote frame received Remote frame received Remot frame receive bits6 message buffers 6 Not remote frame...

Page 536: ...ote frame When set to 0 Clears bits when receiving already completed When set to 1 No effect Setting the RRTRx bit when a remote frame is received RRTRx 1 overrides clearing of the RRTRx bit when 0 is written RRTRx 0 if both occur at the same time The RRTRx bit corresponding to the message buffer x that receives a data frame is cleared RRTRx 0 If message transmitting is completed TCR TCx 1 the RRT...

Page 537: ...curs Receive overrun bit 1 messag buffer1 Not overrun error occurs Overrun error occurs Receive overrun bit 2 messag buffer2 Not overrun error occurs Overrun error occurs Receiv overrun bit 3 messag buffer 3 Not overrun error occurs Overrun error occurs Receiv overrun bit 4 messag buffer 4 Not overrun error occrs Overrun error occurs Receiv overrun bit 5 messag buffer 5 Not overrun error occrs Ove...

Page 538: ...e message buffer that had completed receiving At overrun 1 is set to the ROVRx bit corresponding to the message buffer x where an overrun occurs When set to 0 Cleared when 0 is set to after reception overrun occurred When set to 1 No effect Read using read modify write instructions 1 always read Setting the ROVRx bit when an overrun occurs ROVRx 1 overrides clearing of the ROVRx bit when 0 is writ...

Page 539: ... reception complete interrupt Reception interrupt enable bit 2 Message buffer 2 Disable reception complete interrupt Enables reception complete interrupt Reception interrupt enable bit 3 Message buffer 3 Disable reception complete interrupt Enables reception complete interrupt Reception interrupt enable bit 4 Message buffer 4 Disable reception complete interrupt Enables reception complete interrup...

Page 540: ...ame Function bit0 to bit7 RIE7 to 0 Reception complete interrupt enable bits 7 to 0 These bits enable or disable a reception complete interrupt for the message buffer x When set to 0 Disables reception complete interrupt for message buffer x When set to 1 Enables reception complete interrupt for message buffer x ...

Page 541: ...15 R W AMS7 1 Reset value X X X X X X X X B AMS7 0 AMS6 1 AMS6 0 AMS5 1 AMS5 0 AMS4 1 AMS4 0 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W AMS3 1 Reset value X X X X X X X X B AMS3 0 AMS2 1 AMS2 0 AMS1 1 AMS1 0 AMS0 1 AMS0 0 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W AMSx 0 Acceptance mask select bits x 7 to 0 Full bit comparison is performed Full bit masking is performed 0 1 AMSx 1 0 0 Uses...

Page 542: ...e mask register 0 or 1 The acceptance mask register 0 or 1 AMR0 or AMR1 is used as an acceptance mask filter At collating the setting values of the ID register IDR with the received message ID only the bits set to 0 and corresponding to the AMx bit in the acceptance mask register are compared and the bits set to 1 and corresponding to the AMx bit are masked If the AMSx 1 and AMSx 0 bits are set to...

Page 543: ...ster AMSR bit7 R W AM28 Reset value X X X X X X X X B AM27 BYTE0 BYTE1 BYTE2 BYTE3 AM26 AM25 AM24 AM23 AM22 AM21 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W bit15 R W AM20 Reset value X X X X X X X X B AM19 AM18 AM17 AM16 AM15 AM14 AM13 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W bit7 R W AM12 Reset value X X X X X X X X B AM11 AM10 AM9 AM8 AM7 AM6 AM5 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W 15...

Page 544: ...x with the received message ID When AMx bit set to 1 mask The bits corresponding to the AMx bit set to 1 are masked at collating the acceptance code set in the ID register IDR IDx with the received message ID Note The acceptance mask select register AMSR should be set after disabling the message buffer x to be set BVALR BVALx 0 Setting the acceptance mask select register AMSR with the message buff...

Page 545: ...one message buffer the received message is stored in the message buffer with the smallest number If the same acceptance filter is set in more than one message buffer it can be used as multiple message buffers This provides sufficient time to perform receiving Notes 1 Write by words to the message buffer area and general purpose RAM area At writing by bytes undefined data is written to the upper by...

Page 546: ...R W ID28 Reset value X X X X X X X X B ID27 BYTE0 BYTE1 BYTE2 BYTE3 ID26 ID25 ID24 ID23 ID22 ID21 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W 15 R W ID20 Reset value X X X X X X X X B ID19 ID18 ID17 ID16 ID15 ID14 ID13 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W ID12 Rsest value X X X X X X X X B ID11 ID10 ID9 ID8 ID7 ID6 ID5 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W bit15 R W ID4 Reset val...

Page 547: ...eceive shift register are stored in ID17 to ID0 This will not affect the operation All received message IDs are stored even if specific bits are masked Extended frame format IDER IDEx 1 29 bits from ID28 to ID0 are used Note When using the standard frame format IDER IDEx 0 the bits from ID28 to ID22 cannot be all set to 1 When setting the ID register IDR perform writing by words Writing by bytes i...

Page 548: ...00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 FF FF FF FF FF FF FF BYTE2 00 00 00 00 00 00 00 00 00 00 00 00 01 03 03 06 3F 3F 3F 3F 3F FF FF 00 FC FD FD FE FE FF FF BYTE3 08 10 18 20 28 30 38 40 48 50 F0 F8 00 20 28 40 D8 E0 E8 F0 F8 F0 F8 00 80 00 80 00 80 00 80 1 2 3 4 5 6 7 8 9 10 30 31 32 100 101 200 2043 2044 2045 2046 2047 1 2 3 4 5 6 7 8 9 A 1E 1F 20 64 65 C8 7FB 7FC 7FD 7FE 7FF...

Page 549: ...tion bit0 to bit3 DLC3 to 0 Data length setting bits These bits set the data length byte count of the message to be transmitted or received When data frame transmitted The data length byte count of the transmit message is set When remote frame transmitted The data length byte count of the request message is set When data frame received The data length byte count of the received message is stored W...

Page 550: ... 16 3 25 Functions of Data Register DTR Bit name Function bit0 D7 to 0 BYTE7 to 0 Data bit 7 to 0 The data register DTRx is used only for transmitting or receiving a data frame The transmit message is set up to 8 bytes The received mes sage is stored on an MSB first basis starting with the small message buffer number BYTE0 to BYTE7 The received message is stored The received message is stored on a...

Page 551: ...nsmitting TCR TCx 1 the TCx bit is cleared Reception complete interrupt When message reception is completed 1 is set to the RCx bit in the receive complete register RCR When a reception complete interrupt is enabled RIER RIEx 1 and when RCx 1 a reception complete interrupt is generated When 0 is written to the RCx bit in the reception complete register RCR after the completion of message receiving...

Page 552: ...ntrol status register CSR If a node status transition interrupt is enabled CSR NIE 1 when NT 1 a node status transition interrupt is generated When 0 is written to the NT bit in the control status register the NT bit is cleared Registers and Vector Tables Related to Interrupt of CAN Controller Reference For details on interrupts see 3 5 Interrupt ...

Page 553: ...Explanation of Operation of CAN Controller The following sections provide more details of the operation of CAN controller Transmission of messages See Section 16 5 1 Transmission Reception of messages See Section 16 5 2 Reception Procedures for transmission reception of messages See Section 16 5 3 Procedures for Transmitting and Receiving Reception of multiple messages See Section 16 5 4 Setting M...

Page 554: ...x 0 Reception RTR register is cleared RRTRR RRTRx 0 Transmission complete register is set TCR TCx 1 Cancel transmission TCANR TCANx Clear transmission request register TREQR TREQx 0 Remote frame reception waiting RFWTR RFWTx Remote frame reception RRTRR RRTRx Bus idle state How is fram setting TRTRR TRTRx Transmission seccessed Transmission complete interrupt enabled TIER TIEx 1 Transmit data fram...

Page 555: ...he CAN controller causes contention for a message buffer with another transmitting CAN controller on the CAN bus If arbitration fails or an error occurs during transmitting retransmitting is performed automatically until it succeeds after waiting until the bus goes idle again Selection of frame format When 0 is set to the TRTRx bit in the transmit RTR register a data frame is transmitted When 1 is...

Page 556: ...n the transmission complete register is set The transmission request register and receive RTR register TREQR TREQx 0 RRTRR RRTRx 0 are cleared Generation of transmission interrupt When the TIEx bit in the transmission complete interrupt enable register is set an interrupt request is generated when transmitting is completed TCR TCx 1 ...

Page 557: ... request register TREQR TREQx 0 Setting reception completion register RCR RCx 1 With message buffer X through acceptance filt Reception complete interrupt enabled RIER RIEx 1 Transmission request of remote frame TRTRR TRTRx NO 0 set RCR RCx Received overrun generating ROVRR ROVRx 1 Reception successed YES 1 NO NO TRTRx 0 YES 1 Remote frame Clear received RTR register RRTRR RRTRx 0 Setting received...

Page 558: ...frame received The received message is stored in the ID register IDR and DLC register DLCR The data register DTR remains unchanged More than one message buffer If there is more than one message buffer with the ID that had passed the acceptance filter the message buffer x where the received message is stored is determined under the following conditions Higher priority is given to the message buffer...

Page 559: ...g Message Buffer that Stores Received Message Table 16 5 1 Setting acceptance mask select register AMSx 1 AMSx 0 Acceptance mask x 7 to 0 0 0 Full bit comparison is performed 0 1 Full bit masking is performed 1 0 Using acceptance mask register 0 AMR0 1 1 Using acceptance mask register 1 AMR1 Yes No Start Finish Select one of the smallest message buffer number X Message is not received RCR RCx 0 or...

Page 560: ...not perform transmitting is cancelled Processing for reception of remote frame The reception RTR register is set RRTRR RRTRx 1 If the transmission RTR register is set TRTRR TRTRx 1 the transmission request register is cleared TREQx 0 The request to transmit a remote frame to the message buffer x that does not perform transmitting is cancelled Completing receiving When the received message is store...

Page 561: ... used as the transmit message ID at transmitting and as the acceptance code at receiving Set the ID after disabling the message buffer x BVALR BVALx 0 Setting the ID with the message buffer x enabled may store a message unnecessary received Setting of acceptance filter The acceptance filter used in the message buffer x is set by a combination of the acceptance code and acceptance mask Set the acce...

Page 562: ... AMSR Acceptance mask registers AMR0 1 Transmission request cancel Transmit cancel register TCANR Transmission complete Transmission cancel END TREQx TCx N N 0 Y 1 Y 0 1 0 1 Success of transmitting TCx Setting offrame type Transmit RTR register TRTRx 0 Remote frame receive wait RFWTx 0 data register in transmission data stored Data register DTR Setting of frame type Transmit RTR register TRTRx 1 S...

Page 563: ...and TRTRR TRTRx 0 and starting transmission immediately set the RFWTx bit in the remote frame wait register to 0 When setting the request to transmit a data frame TREQR TREQx 1 and TRTRR TRTRx 0 and starting transmission after waiting until a remote frame is received RRTRR RRTRx 1 set the RFWTx bit in the remote frame wait register to 1 Setting transmission complete interrupt When enabling an inte...

Page 564: ... interrupt is generated After checking the completion of transmission write 0 to the TCx bit in the transmission complete register TCR to clear the transmission complete register TCR When the transmission complete register TCR is cleared the transmission complete interrupt is cancelled When the message is received or stored the held transmission requests are cancelled as follows When a data frame ...

Page 565: ...x 1 set the RIEx bit to 0 START Canceling bus halt HALT 1 Using Message Buffre select Message buffer validating register BVALR Setting reception complete interrupt Receive complete interrupt enable register RIER Setting of bit timing Setting of frame for mat Setting of ID Setting of acceptance filter Bit timing register BTR IDE register IDER ID register IDR Acceptance mask select register AMSR Acc...

Page 566: ...ve register RRTRR is cleared to 0 For remote frame reception 1 is set to the RRTRx bit If a reception interrupt is enabled RIEx of the reception interrupt enable register RIER is 1 an interrupt is generated Process the received message after checking the completion of receiving RCR RCx 1 Check the ROVRx bit in the receive overrun register ROVRR after the completion of processing the received messa...

Page 567: ...549 CHAPTER 16 CAN controller Figure 16 5 6 Example of Reception Interrupt Processing A 0 Received message is read RCx 1 at interrupt generation END A ROVRx ROVRx 0 RCx 0 No Yes ...

Page 568: ...e message buffers to be combined Setting Configuration of Multiple Message Buffer When four messages in the standard frame format are received with doing the acceptance filter of message buffers 5 6 and 7 on the same settings the multiple message buffer operates as shown in the figure Note When the acceptance mask select register is set to full bit comparison AMSR AMSx 1 AMSx 0 00B do not set the ...

Page 569: ...ers5 Message Buffers6 Message Buffers7 RCR ROVRR 0 0 0 0 0 Message receiving Message Buffers 6 memory ID28 to ID18 IDE 0101 1111 001 0 Reception message 0 0 0 0101 1111 000 0101 1111 001 0101 0000 000 Message Buffers5 Message Buffers6 Message Buffers7 RCR ROVRR 0 0 0 0 1 Message receiving Message Buffers 7 memory ID28 to ID18 IDE 0101 1111 010 0 Reception message 0 0 0 0101 1111 000 0101 1111 001 ...

Page 570: ...uffers Work around Operation for suppressing transmission request Do not use BVAL bit for suppressing transmission request use TCAN bit instead of it Operation for composing transmission message For composing a transmission message it is necessary to disable the message buffer by BVAL bit to change contents of ID and IDE registers In this case BVAL bit should reset BVAL 0 after checking if TREQ bi...

Page 571: ...rame format Standard frame format Setting of ID Buffer 0 ID 1 Buffer 5 ID 5 Baud rate 100 Kbps machine clock 16 MHz Acceptance mask selection full bit comparison After entering the bus mode HALT 0 data A0A0H is transmitted A transmission request TREQx 1 is made within the transmission complete interrupt routine to transmit the same data When TREQx is set to start sending the transmission complete ...

Page 572: ...waiting register MOVW TRTRR 0000H Transmission RTR register 0 Transmitting a data frame 1 Transmitting a remote frame MOVW TIER 0020H Transmit complete interrupt enable register Receive Setting MOVW RIER 0001H Receive complete interrupt enable register Bus opening MOV CSR0 80H Control status register HALT 0 sthlt BBS CSR0 0 sthlt HALT 0 wait Transmit data set MOVW DTR5 0A0A0H Message buffer 5 data...

Page 573: ...ions and its operation 17 1 Overview of Address Match Detection Function 17 2 Block Diagram of Address Match Detection Function 17 3 Configuration of Address Match Detection Function 17 4 Explanation of Operation of Address Match Detection Function 17 5 Program Example of Address Match Detection Function ...

Page 574: ...e address of the instruction to be processed next after the instruction currently processed by the program is always held in the address latch through the internal bus The address match detection function always compares the value of the address held in the address latch with that of the address set in the detect address setting registers When these compared values match the next instruction to be...

Page 575: ...ch stores the value of the address output to the internal data bus Address detection control register PACSR The address detection control register enables or disables output of an interrupt at an address match Detect address setting registers PADR0 PADR1 The detect address setting registers set the address that is compared with the value of the address latch PADR0 24bit ReservedReservedReserved AD...

Page 576: ...ch Detection Function Detect address setting registers 1 PADR1 Middle 15 14 bit 13 12 11 10 9 8 Detect address setting registers 1 PADR1 Low 7 6 bit 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Detect address setting registers 0 PADR0 Low bit 15 14 13 12 11 10 9 8 Detect address setting registers 1 PADR1 High bit Detect address setting registers 0 PADR0 High bit Detect address setting registers 0 P...

Page 577: ... 0 0 0 0 0 B 4 5 3 2 1 0 7 6 R W R W R W R W R W R W R W R W AD0E 0 1 Address match detection enable bit 0 Disables the address match PADR0 Enables the address match PADR0 bit1 AD1E 0 1 bit3 0 bit4 Reserved 0 Reserved bit Always set this bit to 0 bit0 Reserved 0 Reserved bit Always set this bit to 0 bit2 Reserved 0 Reserved bit Always set this bit to 0 bit5 Reserved 0 Reserved bit Always set this ...

Page 578: ...ches with the value of address latch at enabling the address match detect operation AD0E 1 the INT9 instruction is immediately executed bit2 Reserved reserved bit Always set this bit to 0 bit3 AD1E Address match detection enable bit 1 The address match detection operation with the detect address setting register 1 PADR1 is enabled or disabled When set to 0 Disables the address match detection oper...

Page 579: ...rupt processing program is executed Detect address setting registers PADR0 PADR1 Figure 17 3 3 Detect address setting registers PADR0 PADR1 R W R W R W R W R W R W R W R W D11 D8 D9 D10 D15 D12 D13 D14 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W D19 D16 D17 D18 D23 D20 D21 D22 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reset value XXXXXXXXB R W ...

Page 580: ...other than the first byte is set to the detect address setting register PADR0 and PADR1 the instruction code is not replaced by INT9 instruction and a program of an interrupt processing is not be performed When the address is set to the second byte or subsequent the address set by the instruction code is replaced by 01 INT9 instruction code and which may cause malfunction The detect address settin...

Page 581: ...ss is set for address match detection PACSR AD0E 0 2 Set the detect address in the detection address setting register 0 PADR0 Set FFH at the higher bits of the detection address setting register 0 PADR0 00H at the middle bits and 1FH at the lower bits 3 Enable the detect address setting register 0 PADR0 where the detect address is set for address match detection PACSR AD0E 1 Program Execution 4 If...

Page 582: ...etection function System Configuration and E2PROM Memory Map System configuration Figure 17 4 2 gives an example of the system configuration using the address match detection function Figure 17 4 2 Example of System Configuration using Address Match Detection Function E2PROM MCU F2 MC16LX Function patch program Pull up resistor External patch program reception connector UART SIN Serial E2PROM inte...

Page 583: ...on address setting registers PADR0 and PADR1 Patch program main body The program executed by the INT9 interrupt processing when the program address matches the detect address is stored Patch program 0 is allocated from any predetermined address Patch program 1 is allocated from the address indicating starting address of patch program 0 total byte count of patch program 0 0 0 0 0 H 0 0 0 1 H 0 0 0 ...

Page 584: ... and 1 are read and set in the detection address setting registers 0 and 1 PADR0 and PADR1 The patch program main body is read according to the byte count of the patch program and written to RAM in the MCU F2MC 16LX The patch program main body is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function Address match detec...

Page 585: ...PROM 000000H FFFFFFH Program error Detectaddresssettingregisters Patch program Setting Detect Address Reset sequence Serial E2PROM Interface Pach program byte count Address detection address Patch program E2PROM 4 2 1 3 ROM RAM 1 Execution of detection address setting of reset sequence and normal program 2 Branch to patch program which expanded in RAM with INT9 interrupt processing by address matc...

Page 586: ...ram branching JMP 000400H Patch program end JMP FF8050H Enables the address match detection PACSR AD0E 1 E2PROM 0000H 0 program address PADR0 Detect address read in E2PROM 0001H to 0003H MCU PADR0 Setting Patch program read in E2PROM 0010H to 008FH MCU 000400H to 00047FH Usual program execution INT9 INT9 NO YES NO YES E2PROM Patch program Detect address High FFH Detect address Middle 80H Detect ad...

Page 587: ...Detect address setting registers 0 Low PADRM EQU 001FF1H Detect address setting registers 0 Middle PADRH EQU 001FF2H Detect address setting registers 0 High Main Program CODE CSEG START Stack pointer SP already initialized MOV PADRL 00H Detect address setting registers 0 Low MOV PADRM 00H Detect address setting registers 0 Middle MOV PADRH 00H Detect address setting registers 0 High MOV I PACSR 00...

Page 588: ...570 CHAPTER 17 Address Match Detecting Function ...

Page 589: ...Function Selection Module This chapter describes the functions and operations of the ROM mirroring function select module 18 1 Overview of ROM Mirroring Function Selection Module 18 2 ROM Mirroring Function Selection Register ROMM ...

Page 590: ... Module Access to FF Bank by ROM Mirroring Function Figure 18 1 2 shows the location in memory when ROM mirroring function allows access to the 00 bank to read ROM data in the FF bank Figure 18 1 2 Access to FF Bank by ROM Mirroring Function Reserved Address Area ROM FF Bank 00 Bank MI Address ROM Mirroring Function Select register ROMM Data Internal Data Bus Reserved Reserved Reserved Reserved Re...

Page 591: ...irroring Function Select Module When ROM mirroring function is enabled Address 1 internal access memory Access prohibited Products Address 1 MB90V495G MB90F897 S In MB90F897 S When the area of FE0000H to FEFFFFH is read data of FF0000H to FFFFFFH can be read FFE000H FFFFFFH FE0000H 010000H 003900H 000100H 0000C0H 000000H 001900H 000900H Peripheral ROM area RAM area Register ROM area Image of FF Ba...

Page 592: ...unction Enables ROM mirroring function bit8 Undefined X Unused Reset Value Write Only W Table 18 2 1 Functions of ROM Mirroring Function Select Register ROMM bit name Function bit8 MI ROM mirroring function select bit This bit enables or disables the ROM mirroring function When set to 0 Disables ROM mirroring function When set to 1 Enables ROM mirroring function When the ROM mirroring function is ...

Page 593: ...19 2 Registers and Sector Bank Configuration of Flash Memory 19 3 Flash Memory Control Status Register FMCS 19 4 Flash Memory Write Control Register FWR0 1 19 5 How to Start Automatic Algorithm of Flash Memory 19 6 Reset Vector Addresses in Flash Memory 19 7 Check the Execution State of Automatic Algorithm 19 8 Details of Programming Erasing Flash Memory ...

Page 594: ... write and reading of the different banks the upper and lower banks can be executed concurrently Features of 512 Kbit Flash Memory 64 Kword x 8 bits 32 Kword x 16 bits 4 K x 4 16 K 8 K x 2 4 K x 4 sector configuration An erase program and a read can be executed concurrently in two banks configuration Uses automatic program algorithm Embedded AlgorithmTM Erase pause restart function Detects complet...

Page 595: ...f 512 Kbit Flash Memory shows the sector configuration of 512 Kbit flash memory The upper and lower addresses of each sector are given in the figure Sector configuration For access from the CPU the FF bank register has SA0 to SA9 Bank configuration The flash memory consists of two banks upper one ranging from SA4 and SA9 and lower one from SA0 and SA3 0 0 0 0 0 0 0 7 6 bit 5 4 3 2 1 0 Flash memory...

Page 596: ...tes SA1 4 Kbytes SA2 4 Kbytes The writer address is equivalent to the CPU address when data is programmed to flash memory by a parallel writer This address is where programming and erasing are performed by a general purpose writer FF4000H FF7FFFH FF8000H FF8FFFH FFC000H FFCFFFH FFD000H FFDFFFH 7 4 0 0 0 H 77FFFH 7 8 0 0 0 H 78FFFH 7C000H 7CFFFH 7D000H 7DFFFH SA7 4 Kbytes SA4 16 Kbytes SA5 16 Kbyte...

Page 597: ...ing erasing next data programming erasing disabled Programming erasing terminated next data programming erasing enabled bit 4 WE 0 1 Flash memory programming erasing enable bit Programming erasing flash memory area disabled Programming erasing flash memory area enabled bit 5 0 1 Flash memory operation flag bit Programming erasing Programming erasing terminated bit 6 INTE 0 1 Flash memory programmi...

Page 598: ...d be set to 0 so as not to accidentally program or erase flash memory To program data into the flash memory after setting FMCS WE to 1 to write enable the flash memory and set the flash memory write control register FWR0 1 When FMCS WE contains 0 for write protection programming into the flash memory is not performed even with the flash memory write control register FWR0 1 write enabling the flash...

Page 599: ... RDYINT and flash memory programming erasing status bit RDY do not change simultaneously A program should be created so as to identify the termination of programming erasing using either the RDYINT bit or RDY bit Automatic algorithm end timing RDY bit RDYINT bit 1 Machine cycle ...

Page 600: ...e sectors Writing 1 to one of the bits enabled to write the corresponding sector Writing 0 to it prevents an accidental write from being executed to the sector Once you have written 0 to the bit therefore you cannot write to the sector even though you write 1 to the bit When you write to the sector again you have to reset the bit Figure 19 4 1 Flash Memory Write Control Register FWR0 1 bit 7 R W S...

Page 601: ... Write enabled 1 status Data can be written to the corresponding sector Accidental write preventive 0 status 0 has been written to the flash memory write control register FWR0 1 where the corresponding sector cannot be write enabled 1 even though 1 is written to the register bit Write protected Write enabled accidental write prevent RST SA0E SA1E SA2E SA3E Initialize Initialize Register write Regi...

Page 602: ...he bit initializes it to 0 write protecting the sector Accidental write preventive function setting bits and flash memory sectors Write protected 0 status 0 has not been written to the flash memory write control register FWR0 1 where you can write 1 to the register bit for each sector to write enable the sector after reset state Write enabled 1 status Data can be written to the corresponding secto...

Page 603: ...must not be used for setting Figure 19 4 3 Sample Procedure for Flash Memory Write Enable Protect Setting and Writing Start Internal address read Program command sequence 1 FFUAAA XXAA 2 FFU554 XX55 3 FFUAAA XXA0 4 Program address Program data Next address FMCS WE bit5 Programming enabled FFWR0 1 Accidental write preventive function setting Accidental write preventive sector 0 writing sector 1 Dat...

Page 604: ... writing the flash memory after setting the FMCS WE bit to 1 in order to be write enabled then set the flash memory write control register FWR0 1 In case of FMCS WE is 0 writing is disabled even if the flash memory write control register FWR0 1 is write enabled ...

Page 605: ...2 must have the same value as RA PA and SA Example When RA FFC48EH U C When SA FF3000H U 3 When PA FF1024H U 1 The chip erase command is accepted only when all sectors have been write enabled The chip erase command is ignored when any of the sector write enable protect bits in the flash memory write control register FWR0 1 contains 0 write protected or accidental write prevented status Write Cycle...

Page 606: ...te enable each required sector before issuing the first command The upper address U bits bits 15 to 12 used when commands are issued must have the same value as RA PA and SA from the first command on If these instructions are not followed commands are not recognized normally requiring that the command sequencer in the flash memory be initialized by a reset ...

Page 607: ...polling In that case fixed reset vector values are read in place of flash memory status flag values Hardwired Reset Vector Addresses Table 19 6 1 lists reset vectors and mode data fixed values Table 19 6 1 Reset Vectors and Mode Data Fixed Values Address Data Fixed Value Reset Vector FFFFDCH 00H FFFFDDH E0H FFFFDEH FFH Mode Data FFFFDFH 00H Note Reset vectors and mode data have values indicated as...

Page 608: ...address of a target sector in flash memory The hardware sequence flag should be output from the bank of only command published side Table 19 7 1 Bit Allocation of Hardware Sequence Flags gives the bit allocation of the hardware sequence flags To identify whether automatic programming chip and sector erasing is in execution or terminated check the hardware sequence flag or the flash memory programm...

Page 609: ...d 0 1 Toggle Stop 0 1 1 Toggle Stop Sector erasing wait Æ Started 0 Toggle 0 0 Toggle Erasing Æ Sector erasing suspended Sector being erased 0 1 Toggle 1 0 1 0 Toggle Sector erasing suspended Æ Resumed Sector being erased 1 0 1 Toggle 0 0 1 Toggle Sector erasing being suspended Sector not being erased DATA 7 DATA 6 DATA 5 DATA 3 DATA 2 Abnormal operation Programming DQ7 Toggle 1 0 1 Chip and secto...

Page 610: ...orithm causes flash memory to output the read value of bit 7 at the address to which read access was performed At chip sector erasing During executing chip and sector erasing algorithms when read access is made to the currently being erasing sector bit 7 of flash memory outputs 0 When chip erasing sector erasing is terminated bit 7 of flash memory outputs 1 Table 19 7 3 State Transition of Data Po...

Page 611: ...ecified by the address signal does not belong to the sector being erased Referring this flag together with the toggle bit flag DQ6 permits a decision on whether flash memory is in the erase suspended state and which sector is being erased Note Read access to the specified address while the automatic algorithm starts is ignored Data reading can be enabled after 1 is set to data polling flag DQ7 Dat...

Page 612: ... for programming and chip erasing sector erasing flash memory outputs bit 6 DATA 6 for the read value of the read address every reading At sector erasing suspension If a read access is made in the sector erasing suspension state flash memory outputs 1 when the read address is the sector being erased and bit 6 DATA 6 for the read value of the read address when the read address is not the sector bei...

Page 613: ...omatic algorithm by the data polling or the toggle bit function is in execution when the timing limit over flag DQ5 outputs 1 programming can be identified as a failure For example when 1 is set to the flash memory address with 1 set the flash memory programming fails In this case the flash memory will be locked and the automatic algorithm will not complete Therefore no valid data is output from t...

Page 614: ...n the sector erasing suspension is set it is ignored until sector erasing is terminated If the sector erasing timer flag DQ3 is 0 flash memory can accept the sector erase command To program the sector erase command check that the sector erasing timer flag DQ3 is 0 If the flag is 1 flash memory may not accept the sector erase command of suspending At sector erasing suspension Read access during sec...

Page 615: ...e after the completion of the algorithm for chip sector erasing flash memory outputs bit 2 DATA 2 of the read address every reading Table 19 7 11 State Transition of Toggle Bit Flag State Change at Normal Operation Operating State Programming Completed Chip and Sector Erasing Completed Wait for Sector Started Sector Erasing Erasing Suspended Sector being Erased Sector Erasing Suspended Resume Sect...

Page 616: ...gramming is performed in the state of the sector erasing suspension flash memory outputs 1 when a continuous read access is started with the sector that is not in the state of the sector erasing suspension The toggle bit 2 flag DQ2 is used together with the toggle bit flag DQ6 to detect that sector erasing is suspended the DQ2 flag performs the toggle operation but the DQ6 flag does not If a read ...

Page 617: ... be started by programming the command sequence of read reset programming chip erasing sector erasing sector erasing suspension and erasing resumption from CPU to flash memory Programming flash memory from the CPU should always be performed continuously The termination of the automatic algorithm can be checked by the data polling function After normal termination it returns to the read reset state...

Page 618: ... the other is executed at three times bus operation the command sequence of both is essentially the same Since the read reset state is the initial state for flash memory flash memory always enters this state after power on and at the normal termination of command The read reset state is also described as the wait state for command input In the read reset state a read access to flash memory enables...

Page 619: ...g algorithm DQ7 or toggling DQ6 is not terminated and the flash memory is considered faulty the timing limit over flag DQ5 is determined as an error When data is read in the read reset state the bit data remains 0 To return the bit data to 1 from 0 erase flash memory data All commands are ignored during automatic programming If a hardware reset occurs during programming data being programmed to ad...

Page 620: ...FFUAAA XXA0 4 Program address Program data Next address FMCS WE bit5 Programming enabled FFWR0 1 Accidental write preventive function setting Accidental write preventive sector 0 writing sector 1 Data polling DQ7 Data Data Timing limit DQ5 1 0 Last address YES NO FMCS WE bit5 Programming enabled Data Data Internal address read Data polling DQ7 Programming error Completed ...

Page 621: ...asing is started at completion of the sixth programming cycle Before chip erasing the user need not perform programming to flash memory During execution of the automatic erasing algorithm flash memory automatically programs 0 before erasing all cells Notes on Chip Erasure The chip erase command is accepted only when all sectors have been write enabled The chip erase command is ignored when any of ...

Page 622: ...or erase code has been programmed That is when erasing more than one sector simultaneously the address of erase sector address and the sector code must be input within 50 µs If the sector erase code is input 50 µs or later it cannot be accepted Whether continuous programming of the sector erase code is enabled can be checked by the sector erase timer flag DQ3 In this case the address from which th...

Page 623: ...ernal address read Is any other erase sector Timing limit DQ5 1 Completed 0 Last sector FMCS WE bit 5 Programming enabled Erasing error Internal address read Sector erase timer DQ3 1 0 Internal address read 2 Internal address read 1 Toggle bit DQ6 Data 1 Data 2 Toggle bit DQ6 Data 1 Data 2 NO NO NO NO YES YES YES YES FFWR0 1 Accidental write preventive function setting Accidental write preventive ...

Page 624: ...nd is only enabled during the sector erasing period including the erasing wait time it is ignored during the chip erasing period or during programming The sector erasing suspend command is executed when the sector erasing suspend code B0H is programmed Arbitrary address in flash memory should be set for address If the sector erasing suspend command is executed during sector erasing pause the succe...

Page 625: ... can be resumed by continuously transmitting the sector erase resume command in the command sequence table from CPU to flash memory The sector erase resume command resumes sector erasing suspended by the sector erase suspend command This command is executed by writing the erase resume code 30H In this case even address in the specified sector for erase area is specified Inputting the sector erase ...

Page 626: ...608 CHAPTER 19 512 KBIT FLASH MEMORY ...

Page 627: ...20 DUAL OPERATION FLASH This chapter describes the functions and operation of Dual Operation Flash 20 1 Overview of Dual Operation Flash 20 2 Register for Dual Operation Flash 20 3 Operation of Dual Operation Flash ...

Page 628: ...ecution to program data into the flash memory resulting in reduced download time and no need to consider power shutdown for RAM data maintenance Also the minimum sectors are as compact as four kilobytes that can be handled easily as program data areas Features of Dual Operation Flash Tow bank configuration enabling simultaneous execution of an erase program and reading Minimum sectors in four kilo...

Page 629: ...ctor switching register SSR0 Table 20 2 1 the function of the sector switching register SSR0 Bit name Function Bit7 Bit6 Reserved Reserved bit Be sure to set to 0 Bit5 Bit1 Undefined bit At a read The value is undefined At a write The operation is not affected Bit0 SEN0 The SEN0 bit switches access from the CPU for reprogramming the upper bank from SA9 containing the interrupt vector to SA3 in the...

Page 630: ...FF0000H FF0FFFH FF1000H FF1FFFH FF2000H FF2FFFH FF3000H FF3FFFH FF4000H FF7FFFH FF8000H FFBFFFH FFC000H FFCFFFH FFD000H FFDFFFH FFE000H FFEFFFH FFF000H FFFFFFH SA0 4K SA1 4K SA2 4K SA3 4K SA4 16K SA5 16K SA6 4K SA7 4K SA8 4K SA9 4K SA0 4K SA1 4K SA2 4K SA9 4K SA4 16K SA5 16K SA6 4K SA7 4K SA8 4K SA3 4K Hard Wired Reset Vector FFE000H Interrupt Vector CPU address SEN0 0 SEN0 1 Interrupt Vector ...

Page 631: ... accessed to read the interrupt vector data The same data as SA3 and SA9 must be before setting the sector switching register SSR0 Sector switching register SSR0 setting procedure Figure20 3 1 illustrates the procedure of setting the sector switching register SSR0 The SEN0 bit must be set to 1 before reprogramming of data in the upper bank Note also that it is not allowed to make any change to the...

Page 632: ...is prohibited in interrupt routine If there are two or more write erase routines the next write erase routine should be execution after the an write erase routine step by step During write erase operation to flash memory the state transferring from write erase mode main clock mode PLL clock mode sub clock mode is prohibited The state transfers after write erase operation ...

Page 633: ...615 APPENDIX The appendices provide the I O map and outline of instructions APPENDIX A Instructions APPENDIX B Register Index APPENDIX C Pin Function Index APPENDIX D Interrupt Vector Index ...

Page 634: ...e instructions used by the F2MC 16LX A 1 Instruction Types A 2 Addressing A 3 Direct Addressing A 4 Indirect Addressing A 5 Execution Cycle Count A 6 Effective Address Field A 7 How to Read the Instruction List A 8 F2MC 16LX Instruction List A 9 Instruction Map ...

Page 635: ...ctions byte word or long word 11 unsigned multiplication division instructions word or long word 11 signed multiplication division instructions word or long word 39 logic instructions byte or word 6 logic instructions long word 6 sign inversion instructions byte or word 1 normalization instruction long word 18 shift instructions byte word or long word 50 branch instructions 6 accumulator operation...

Page 636: ...address addr24 I O direct io Abbreviated direct address dir Direct address addr16 I O direct bit address io bp Abbreviated direct bit address dir bp Direct bit address addr16 bp Vector address vct Register indirect RWj j 0 to 3 Register indirect with p os t increment RWj j 0 to 3 Register indirect with displacement RWi disp8 i 0 to 7 RWj disp16 j 0 to 3 Long register indirect with displacement RLi...

Page 637: ...6 R6 RW6 RL3 07 R7 RW7 RL3 08 RW0 Register indirect DTB 09 RW1 DTB 0A RW2 ADB 0B RW3 SPB 0C RW0 Register indirect with post increment DTB 0D RW1 DTB 0E RW2 ADB 0F RW3 SPB 10 RW0 disp8 Register indirect with 8 bit displacement DTB 11 RW1 disp8 DTB 12 RW2 disp8 ADB 13 RW3 disp8 SPB 14 RW4 disp8 DTB 15 RW5 disp8 DTB 16 RW6 disp8 ADB 17 RW7 disp8 SPB 18 RW0 disp16 Register indirect with 16 bit displac...

Page 638: ...ssing MOVW A 01212H This instruction stores the operand value in A Before execution A 2 2 3 3 4 4 5 5 After execution A 4 4 5 5 1 2 1 2 Some instructions transfer AL to AH Table A 3 1 Direct addressing registers General purpose register Byte R0 R1 R2 R3 R4 R5 R6 R7 Word RW0 RW1 RW2 RW3 RW4 R5W RW6 RW7 Long word RL0 RL1 RL2 RL3 Special purpose register Accumulator A AL Pointer SP 1 Bank PCB DTB USB...

Page 639: ... Bits 23 to 16 of the address are specified by the program bank register PCB Figure A 3 3 Example of direct branch addressing addr16 MOV R0 A Before execution A 0 7 1 6 2 5 3 4 After execution A 0 7 1 6 2 5 6 4 This instruction transfers the eight low order bits of A to the general purpose register R0 R0 Memory space 3 4 R0 Memory space JMP 3B20H Before execution PC 3 C 2 0 After execution This in...

Page 640: ... accessed regardless of the data bank register DTB and direct page register DPR A bank select prefix for bank addressing is invalid if specified before an instruction using I O direct addressing Figure A 3 5 Example of I O direct addressing io JMPP 333B20H Before execution PC 3 C 2 0 After execution PCB 4 F PC 3 B 2 0 PCB 3 3 4F3C23H 3 3 4F3C22H 3 B 4F3C21H 2 0 4F3C20H 6 3 JMPP 333B20H Memory spac...

Page 641: ...to 23 are specified by the data bank register DTB A prefix instruction for access space addressing is invalid for this mode of addressing Figure A 3 7 Example of direct addressing addr16 4 4 5 5 1 2 1 2 6 6 6 6 1 2 4 4 5 5 1 2 1 2 7 7 DTB 7 7 DTB 776620H 776620H Before execution After execution MOVW S 20H A Memory space Memory space A A This instruction writes the contents of the eight low order b...

Page 642: ...are specified by the direct page register DPR Address bits 16 to 23 are specified by the data bank register DTB Bit positions are indicated by bp where the larger number indicates the most significant bit MSB and the lower number indicates the least significant bit LSB Figure A 3 9 Example of abbreviated direct bit addressing dir bp 0 0 0 1 0000C1H 0000C1H Before execution After execution SETB I 0...

Page 643: ...erand to indicate the branch destination address There are two sizes for vector numbers 4 bits and 8 bits Vector addressing is used for a subroutine call or software interrupt instruction Figure A 3 11 Example of vector addressing vct SETB 2222H 0 5 5 DTB 5 5 0 0 0 1 DTB 552222H 552222H Before execution After execution Memory space Memory space This instruction sets bits by direct bit addressing C...

Page 644: ... Vector address H CALLV 0 XXFFFEH XXFFFFH CALLV 1 XXFFFCH XXFFFDH CALLV 2 XXFFFAH XXFFFBH CALLV 3 XXFFF8H XXFFF9H CALLV 4 XXFFF6H XXFFF7H CALLV 5 XXFFF4H XXFFF5H CALLV 6 XXFFF2H XXFFF3H CALLV 7 XXFFF0H XXFFF1H CALLV 8 XXFFEEH XXFFEFH CALLV 9 XXFFECH XXFFEDH CALLV 10 XXFFEAH XXFFEBH CALLV 11 XXFFE8H XXFFE9H CALLV 12 XXFFE6H XXFFE7H CALLV 13 XXFFE4H XXFFE5H CALLV 14 XXFFE2H XXFFE3H CALLV 15 XXFFE0H ...

Page 645: ...ister RWj as an address After operand operation RWj is incremented by the operand size 1 for a byte 2 for a word or 4 for a long word Address bits 16 to 23 are indicated by the data bank register DTB when RW0 or RW1 is used system stack bank register SSB or user stack bank register USB when RW3 is used or additional data bank register ADB when RW2 is used If the post increment results in the addre...

Page 646: ...ack bank register USB when RW3 or RW7 is used or additional data bank register ADB when RW2 or RW6 is used Figure A 4 3 Example of register indirect addressing with offset RWi disp8 i 0 to 7 RWj disp16 j 0 to 3 MOVW A RW1 0 7 1 6 A D 3 0 F 2 5 3 4 RW1 F F E E 2 5 3 4 A D 3 1 1 F F E E RW1 7 8 DTB 7 8 DTB 78D310H 78D30FH Before execution After execution Memory space This instruction reads data by r...

Page 647: ...each of the following instructions is not deemed to be next instruction address disp16 DBNZ eam rel DWBNZ eam rel CBNE eam imm8 rel CWBNE eam imm16 rel MOV eam imm8 MOVW eam imm16 Figure A 4 5 Example of program counter indirect addressing with offset PC disp16 MOVW A RL2 25H 0 7 1 6 A 2 5 3 4 F 3 8 2 4 B 0 2 RL2 F F E E 2 5 3 4 A F F E E F 3 8 2 4 B 0 2 RL2 824B28H 824B27H 25H Before execution Af...

Page 648: ...d and the excess part is ignored and therefore the address is contained within a 64 kilobyte bank This addressing is used for both conditional and unconditional branch instructions Address bits 16 to 23 are indicated by the program bank register PCB Figure A 4 7 Example of program counter relative branch addressing rel MOVW A RW1 RW7 0 7 1 6 A D 3 0 F 2 5 3 4 RW1 F F E E 2 5 3 4 A D 3 0 F F F E E ...

Page 649: ...cted when the corresponding bit is 1 and deselected when the bit is 0 POPW RW0 RW4 3 4 F A SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 0 4 0 3 34FDH 34FCH 34FEH 0 2 0 1 34FBH 34FAH SP 3 4 F E SP 0 1 0 2 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 0 3 0 4 0 4 0 3 34FDH 34FCH 34FEH 0 2 0 1 34FBH 34FAH SP Before execution After execution Memory space Memory space This instruction transfers memory data indicated by the SP...

Page 650: ...d by the program bank register PCB For the Jump Context JCTX instruction however address bits 16 to 23 are specified by the data bank register DTB This addressing is used for unconditional branch instructions Figure A 4 11 Example of accumulator indirect branch addressing A MOVW A A 0 7 1 6 A 2 5 3 4 DTB F F E E 0 7 1 6 A F F E E DTB B B B B BB2535H BB2534H Before execution After execution Memory ...

Page 651: ...ndirect specification branch addressing eam JMP RW0 0 8 3 C 2 0 PC 7 F 4 8 PW0 4 F PCB 2 1 DTB 3 B 2 0 PC 7 F 4 8 PW0 4 F PCB 2 1 DTB 4F3C21H 7 3 4F3C20H 3 B 217F49H 2 0 217F48H JMP RW0 4F3B20H Before execution After execution Memory space This instruction causes an unconditional branch by register indirect addressing Next instruction JMP RW0 0 0 3 C 2 0 PC 3 B 2 0 PW0 4 F PCB 3 B 2 0 PC 3 B 2 0 P...

Page 652: ...neral purpose register internal ROM internal RAM internal I O unit or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits in the low power consumption mode control register For the cycle count required for instruction execution in CPU intermittent operation mode therefore add the corresponding access count x halt cycle count as a correction v...

Page 653: ...B correction value in A 8 F2MC 16LX Instruction List 2 When an external data bus is used the number of cycles during which an instruction is made to wait by ready signal input or automatic ready must also be added Table A 5 3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory 2 External data bus 16 bits 3 External data bus 8 ...

Page 654: ...rect Individual parts correspond to the byte word and long word types in order from the left 01 R1 RW1 RL0 02 R2 RW2 RL1 03 R3 RW3 RL1 04 R4 RW4 RL2 05 R5 RW5 RL2 06 R6 RW6 RL3 07 R7 RW7 RL3 08 RW0 Register indirect 0 09 RW1 0A RW2 0B RW3 0C RW0 Register indirect with post increment 0 0D RW1 0E RW2 0F RW3 10 RW0 disp8 Register indirect with 8 bit displacement 1 11 RW1 disp8 12 RW2 disp8 13 RW3 dis...

Page 655: ...dex 0 1D RW1 RW7 Register indirect with index 0 1E PC disp16 PC indirect with 16 bit displacement 2 1F addr16 Direct address 2 Each byte count of the extended address part applies to in the byte count column in A 8 F2MC 16LX Instruction List Table A 6 1 Effective Address Field 2 2 Code Representation Address format Byte count of extended address port number of byte ...

Page 656: ...ion The number is used to calculate the correction value for CPU intermittent operation B Indicates the correction value used to calculate the actual number of cycles during instruction execution The actual number of cycles during instruction execution can be determined by adding the value in the column to this value Operation Indicates the instruction operation LH Indicates the special operation ...

Page 657: ...rd 32 bits of AL and AH AH 16 high order bits of A AL 16 low order bits of A SP Stack pointer USP or SSP PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register SSB or USB DPR Direct page register brg1 DTB ADB SSB USB DPR PCB SPB brg2 DTB ADB SSB USB DPR SPB Ri ...

Page 658: ... of 8 bit immediate data disp8 8 bit displacement disp16 16 bit displacement bp Bit offset vct4 Vector number 0 to 15 vct8 Vector number 0 to 255 b Bit address rel PC relative branch ear Effective addressing code 00 to 07 eam Effective addressing code 08 to 1F rlst Register list Table A 7 2 Explanation on Symbols in the Instruction List 2 2 Representation Explanation ...

Page 659: ...ddr16 3 4 0 b byte A addr16 X MOVX A Ri 2 2 1 0 byte A Ri X MOVX A ear 2 2 1 0 byte A ear X MOVX A eam 2 3 a 0 b byte A eam X MOVX A io 2 3 0 b byte A io X MOVX A imm8 2 2 0 0 byte A imm8 X MOVX A A 2 3 0 b byte A A X MOVX A RWi disp8 2 5 1 b byte A RWi disp8 X MOVX A RLi disp8 3 10 2 b byte A RLi disp8 X MOV dir A 2 3 0 b byte dir A MOV addr16 A 3 4 0 b byte addr16 A MOV Ri A 1 2 1 0 byte Ri A MO...

Page 660: ...addr16 A 3 4 0 c word addr16 A MOVW SP A 1 1 0 0 word SP A MOVW RWi A 1 2 1 0 word RWi A MOVW ear A 2 2 1 0 word ear A MOVW eam A 2 3 a 0 c word eam A MOVW io A 2 3 0 c word io A MOVW RWi disp8 A 2 5 1 c word RWi disp8 A MOVW RLi disp8 A 3 10 2 c word RLi disp8 A MOVW RWi ear 2 3 2 0 word RWi ear MOVW 2 4 a 1 c word RWi eam MOVW ear Rwi 2 4 2 0 word ear RWi MOVW eam Rwi 2 5 a 1 c word eam RWi MOVW...

Page 661: ... 2 4 a 0 b byte A A eam Z SUB ear A 2 3 2 0 byte ear ear A SUB eam A 2 5 a 0 2 x b byte eam eam A SUBC A 1 2 0 0 byte A AH AL C Z SUBC A ear 2 3 1 0 byte A A ear C Z SUBC A eam 2 4 a 0 b byte A A eam C Z SUBDC A 1 3 0 0 byte A AH AL C decimal Z ADDW A 1 2 0 0 word A AH AL ADDW A ear 2 3 1 0 word A A ear ADDW A eam 2 4 a 0 c word A A eam ADDW A imm16 3 2 0 0 word A A imm16 ADDW ear A 2 3 2 0 word e...

Page 662: ...3 2 0 byte ear ear 1 DEC eam 2 5 a 0 2 x b byte eam eam 1 INCW ear 2 3 2 0 word ear ear 1 INCW eam 2 5 a 0 2 x c word eam eam 1 DECW ear 2 3 2 0 word ear ear 1 DECW eam 2 5 a 0 2 x c word eam eam 1 INCL ear 2 7 4 0 long ear ear 1 INCL eam 2 9 a 0 2 x d long eam eam 1 DECL ear 2 7 4 0 long ear ear 1 DECL eam 2 9 a 0 2 x d long eam eam 1 Table A 8 5 11 Compare instructions byte word long word Mnemon...

Page 663: ...7 long A word eam quotient word A remainder word eam MULL A 1 8 0 0 byte AH byte AL word A MULL A ear 2 9 1 0 byte A byte ear word A MULL A eam 2 10 0 b byte A byte eam word A MULEY A 1 11 0 0 word AH word AL Long A MULEY A ear 2 12 1 0 word A word ear Long A MULEY A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 7 Overflow 15 Normal 2 4 Division by 0 8 Overflow 16 Normal 3 6 a Division by ...

Page 664: ...0 byte AH byte AL word A MUL A ear 2 9 1 0 byte A byte ear word A MUL A eam 2 10 0 b byte A byte eam word A MULW A 2 11 0 0 word AH word AL Long A MULW A ear 2 12 1 0 word A word ear Long A MULW A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 8 or 18 Overflow 18 Normal 2 4 Division by 0 11 or 22 Overflow 23 Normal 3 5 a Division by 0 12 a or 23 a Overflow 24 a Normal 4 When dividend is pos...

Page 665: ...eam R XOR ear A 2 3 2 0 byte ear ear xor A R XOR eam A 2 5 a 0 2 x b byte eam eam xor A R NOT A 1 2 0 0 byte A not A R NOT ear 2 3 2 0 byte ear not ear R NOT eam 2 5 a 0 2 x b byte eam not eam R ANDW A 1 2 0 0 word A AH and A R ANDW A imm16 3 2 0 0 word A A and imm16 R ANDW A ear 2 3 1 0 word A A and ear R ANDW A eam 2 4 a 0 c word A A and eam R ANDW ear A 2 3 2 0 word ear ear and A R ANDW eam A 2...

Page 666: ...g A A and eam R ORL A ear 2 6 2 0 long A A or ear R ORL A eam 2 7 a 0 d long A A or eam R XORL A ear 2 6 2 0 long A A xor ear R XORL A eam 2 7 a 0 d long A A xor eam R Table A 8 10 6 Sign inversion instructions byte word Mnemonic RG B Operation L H A H I S T N Z V C R M W NEG A 1 2 0 0 byte A 0 A X NEG ear 2 3 2 0 byte ear 0 ear NEG eam 2 5 a 0 2 x b byte eam 0 eam NEGW A 1 2 0 0 word A 0 A NEGW e...

Page 667: ... a 0 2 x b byte eam With left rotation carry ASR A R0 2 1 1 0 byte A Arithmetic right shift A 1 bit LSR A R0 2 1 1 0 byte A Logical right barrel shift A R0 LSL A R0 2 1 1 0 byte A Logical left barrel shift A R0 ASRW A 1 2 0 0 word A Arithmetic right shift A 1 bit LSRW A SHRW A 1 2 0 0 word A Logical right shift A 1 bit R LSLW A SHLW A 1 2 0 0 word A Logical left shift A 1 bit ASRW A R0 2 1 1 0 wor...

Page 668: ...rel 2 1 0 0 Branch on C or Z 1 BHI rel 2 1 0 0 Branch on C or Z 0 BRA rel 2 1 0 0 Unconditional branch JMP A 1 2 0 0 word PC A JMP addr16 3 3 0 0 word PC addr16 JMP ear 2 3 1 0 word PC ear JMP eam 2 4 a 0 c word PC eam JMPP ear 3 2 5 2 0 word PC ear PCB ear 2 JMPP eam 3 2 6 a 0 d word PC eam PCB eam 2 JMPP addr24 4 4 0 0 word PC ad24 0 15 PCB ad24 16 23 CALL ear 4 2 6 1 c word PC ear CALL addr16 5...

Page 669: ... eam 1 eam not equal to 0 INT vct8 2 20 0 8 x c Software interrupt R S INT addr16 3 16 0 6 x c Software interrupt R S INTP addr24 4 17 0 6 x c Software interrupt R S INT9 1 20 0 8 x c Software interrupt R S RETI 1 8 0 7 Return from interrupt LINK imm8 2 6 0 c Saves the old frame pointer in the stack upon entering the function then sets the new frame pointer and reserves the local pointer area UNLI...

Page 670: ...CR CCR or imm8 MOV RP imm8 2 2 0 0 byte RP imm8 MOV ILM imm8 2 2 0 0 byte ILM imm8 MOVEA RWi ear 2 3 1 0 word RWi ear MOVEA RWi eam 2 2 a 1 0 word RWi eam MOVEA A ear 2 1 0 0 word A ear MOVEA A eam 2 1 a 0 0 word A eam ADDSP imm8 2 3 0 0 word SP ext imm8 ADDSP imm16 3 3 0 0 word SP imm16 MOV A brg1 2 1 0 0 byte A brg1 Z MOV brg2 A 2 1 0 0 byte brg2 A NOP 1 1 0 0 No operation ADB 1 1 0 0 Prefix cod...

Page 671: ...dr16 bp b 0 CLRB io bp 3 7 0 2 x b bit io bp b 0 BBC dir bp rel 4 1 0 b Branch on dir bp b 0 BBC addr16 bp rel 5 1 0 b Branch on addr16 bp b 0 BBC io bp rel 4 2 0 b Branch on io bp b 0 BBS dir bp rel 4 1 0 b Branch on dir bp b 1 BBS addr16 bp rel 5 1 0 b Branch on addr16 bp b 1 BBS io bp rel 4 1 0 b Branch on io bp b 1 SBBS addr16 bp rel 5 3 0 2 x b Branch on addr16 bp b 1 bit 1 WBTS io bp 3 4 0 5...

Page 672: ...yte search AH AL counter RW0 FILS FILSI 2 6m 6 5 3 byte fill AH AL counter RW0 MOVSW MOVSWI 2 2 5 6 word transfer AH AL counter RW0 MOVSWD 2 2 5 6 word transfer AH AL counter RW0 SCWEQ SCWEQI 2 1 5 7 word search AH AL counter RW0 SCWEQD 2 1 5 7 word search AH AL counter RW0 FILSW FILSWI 2 6m 6 5 6 word fill AH AL counter RW0 1 5 when RW0 is 0 4 7 x RW0 when the counter expires or 7n 5 when a match...

Page 673: ...nstruction such as the NOP instruction that ends in one byte is completed within the basic page An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 map When it references byte 1 and can check byte 1 by referencing Figure A 9 2 shows correspondence between actual instruction code and instruction map Basic page map Bit operation instructions Charact...

Page 674: ...ction Instruction code Some instructions do not contain byte 2 1 The extended page map is a generic name of maps for bit operation instructions character string operation instructions 2 byte instructions and ea instructions Actually there are multiple extended page maps for each type of instructions Table A 9 1 example of an instruction code Instruction Byte 1 from basic page map Byte 2 from exten...

Page 675: ...p Bit operation instruction Character string opera tion instruction 2 byte instruction ea instruc tion 1 ea instruc tion 2 ea instruc tion 3 ea instruc tion 4 ea instruc tion 5 ea instruc tion 6 ea instruc tion 7 ea instruc tion 8 ea instruc tion 9 Ri ea ...

Page 676: ...658 APPENDIX Table A 9 3 Bit Operation Instruction Map first byte 6CH ...

Page 677: ...659 APPENDIX A Instructions Table A 9 4 Character String Operation Instruction Map first byte 6EH ...

Page 678: ...660 APPENDIX Table A 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...

Page 679: ...661 APPENDIX A Instructions Table A 9 6 ea Instruction 1 first byte 70H Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited ...

Page 680: ...662 APPENDIX Table A 9 7 ea Instruction 2 first byte 71H ...

Page 681: ...663 APPENDIX A Instructions Table A 9 8 ea Instruction 3 first byte 72H ...

Page 682: ...664 APPENDIX Table A 9 9 ea Instruction 4 first byte 73H ...

Page 683: ...665 APPENDIX A Instructions Table A 9 10 ea Instruction 5 first byte 74H ...

Page 684: ...666 APPENDIX Table A 9 11 ea Instruction 6 first byte 75H ...

Page 685: ...667 APPENDIX A Instructions Table A 9 12 ea Instruction 7 first byte 76H ...

Page 686: ...668 APPENDIX Table A 9 13 ea Instruction 8 first byte 77H ...

Page 687: ...669 APPENDIX A Instructions Table A 9 14 ea Instruction 9 first byte 78H ...

Page 688: ...670 APPENDIX Table A 9 15 MOVEA RWi ea Instruction first byte 79H ...

Page 689: ...671 APPENDIX A Instructions Table A 9 16 MOV Ri ea Instruction first byte 7AH ...

Page 690: ...672 APPENDIX Table A 9 17 MOVW RWi ea Instruction first byte 7BH ...

Page 691: ...673 APPENDIX A Instructions Table A 9 18 MOV ea Ri Instruction first byte 7CH ...

Page 692: ...674 APPENDIX Table A 9 19 MOVW ea Rwi Instruction first byte 7DH ...

Page 693: ...675 APPENDIX A Instructions Table A 9 20 XCH Ri ea Instruction first byte 7EH ...

Page 694: ...676 APPENDIX Table A 9 21 XCHW RWi ea Instruction first byte 7FH ...

Page 695: ... 000012H DDR2 Port 2 direction register 00000000B port 2 170 000013H DDR3 Port 3 direction register 000X0000B port 3 175 000014H DDR4 Port 4 direction register XXX00000B Port 4 180 000015H DDR5 Port 5 direction register 00000000B Port 5 186 000016H to 00001AH Reserved area 00001BH ADER Analog input enable register 11111111B 8 10 bit A D converter 365 00001CH to 00001FH Reserved area 000020H SMR0 S...

Page 696: ...DCS A D control status register 00000000B 8 10 bit A D converter 359 000035H 00000000B 356 000036H ADCR A D data register XXXXXXXXB 364 000037H 00101XXXB 362 000038H to 00003EH Reserved area 00003FH PSCCR PLL subclock control register for extension XXXXX000B Clock 116 000040H PPGC0 PPG0 operation mode control register 0X000XX1B 8 16 bit PPG timer 0 1 301 000041H PPGC1 PPG operation mode control re...

Page 697: ...ea 00005AH IPCP2 Input capture data register2 XXXXXXXXB 16 bit I O timer 235 00005BH XXXXXXXXB 00005CH IPCP3 Input capture data registers IPCP0 to IPCP3 3 XXXXXXXXB 235 00005DH XXXXXXXXB 00005EH to 000065H Reserved area 000066H TMCSR0 Timer control status register TMCSR 00000000B 16 bit reload timer 0 257 000067H XXXX0000B 255 000068H TMCSR1 00000000B 16 bit reload timer 1 257 000069H XXXX0000B 25...

Page 698: ...eption complete interrupt enable register 00000000B CAN controller 521 00008FH to 00009DH Reserved area 00009EH PACSR Address detection control register 00000000B Address match detecting function 559 00009FH DIRR Delayed interrupt request generate cancel register XXXXXXX0B Delayed interrupt generation module 325 0000A0H LPMCR Low power consumption mode control register 00011000B Low power Consumpt...

Page 699: ...ster 05 00000111B 0000B6H ICR06 Interrupt control register 06 00000111B 0000B7H ICR07 Interrupt control register 07 00000111B 0000B8H ICR08 Interrupt control register 08 00000111B 0000B9H ICR09 Interrupt control register 09 00000111B 0000BAH ICR10 Interrupt control register 10 00000111B 0000BBH ICR11 Interrupt control register 11 00000111B 0000BCH ICR12 Interrupt control register 12 00000111B 0000...

Page 700: ...6 bit reload timer 1 259 260 003903H XXXXXXXXB 003904H to 003909H Reserved area 00390AH FWR0 Flash memory write control register 0 00000000B Dual FLASH 582 00390BH FWR1 Flash memory write control register 1 00000000B 00390CH SSR0 Sector switching register 00XXXXX0B 611 00390DH to 00390FH Reserved area 003910H PRLL0 PPG0 reload register L XXXXXXXXB 8 16 bit PPG timer 307 003911H PRLH0 PPG0 reload r...

Page 701: ... 003C00H to 003C0FH RAM general purpose RAM 003C10H to 003C13H IDR0 ID register 0 XXXXXXXXB to XXXXXXXXB CAN controller 528 003C14H to 003C17H IDR1 ID register 1 XXXXXXXXB to XXXXXXXXB Table B 1 Register Index 7 10 Address Register Abbrevia tion Register Name Reset Value Resource Name Page Number ...

Page 702: ... to XXXXXXXXB 003C30H 003C31H DLCR0 DLC register 0 XXXXXXXXB XXXXXXXXB 531 003C32H 003C33H DLCR1 DLC register 1 XXXXXXXXB XXXXXXXXB 003C34H 003C35H DLCR2 DLC register 2 XXXXXXXXB XXXXXXXXB 003C36H 003C37H DLCR3 DLC register 3 XXXXXXXXB XXXXXXXXB 003C38H 003C39H DLCR4 DLC register 4 XXXXXXXXB XXXXXXXXB 003C3AH 003C3BH DLCR5 DLC register 5 XXXXXXXXB XXXXXXXXB 003C3CH 003C3DH DLCR6 DLC register 6 XXX...

Page 703: ...XB to XXXXXXXXB 003C78H to 003C7FH DTR7 Data register 7 XXXXXXXXB to XXXXXXXXB 003C80H to 003CFFH Reserved area 003D00H 003D01H CSR Control status register 0XXXX001B 00XXX000B CAN controller 488 486 003D02H LEIR Last event indicate register 000XX000B 491 003D03H Reserved area 003D04H 003D05H RTEC Receive transmit error counter 00000000B 00000000B CAN controller 493 003D06H 003D07H BTR Bit timing r...

Page 704: ...03D17H AMR0 Acceptance mask register 0 XXXXXXXXB to XXXXXXXXB CAN controller 525 003D18H to 003D1BH AMR1 Acceptance mask register 1 XXXXXXXXB to XXXXXXXXB 003D1CH to 003DFFH Reserved area 003E00H to 003EFFH Reserved area 003FF0H to 003FFFH Reserved area Explanation of reset value 0 The reset value of this bit is 0 1 The reset value of this bit is 1 X The reset value of this bit is unfixed Do not w...

Page 705: ...69 TIN0 Event input pin for reload timer 0 252 249 13 P21 D General purpose I O ports 167 169 TOT0 Event output pin for reload timer 0 252 249 14 P22 D General purpose I O ports 167 169 TIN1 Event input pin for reload timer 1 252 249 15 P23 D General purpose I O ports 167 169 TOT1 Event output pin for reload timer 1 252 249 16 to 19 P24 to P27 D General purpose I O ports 167 169 INT4 to INT7 Exter...

Page 706: ... for CAN controller 482 479 41 P44 D General purpose I O ports 178 179 RX Receive input pin for CAN controller 482 479 42 P30 D General purpose I O ports 173 174 SOT0 Serial data output pin 387 384 43 P31 D General purpose I O ports 173 174 SCK0 Serial clock input output pin for UART0 387 384 44 P32 H General purpose I O ports 173 174 SIN0 Serial data input pin 387 384 45 P33 D General purpose I O...

Page 707: ...FFFBDH FFFFBEH 199 17 16 bit reload timer 0 ICR03 0000B3H FFFFB8H FFFFB9H FFFFBAH 261 18 8 10 bit A D converter FFFFB4H FFFFB5H FFFFB6H 367 19 16 bit free run timer overflow ICR04 0000B4H FFFFB0H FFFFB1H FFFFB2H 236 20 Reserved FFFFACH FFFFADH FFFFAEH 21 Reserved ICR05 0000B5H FFFFA8H FFFFA9H FFFFAAH 22 PPG timer channel 0 1 underflow FFFFA4H FFFFA5H FFFFA6H 308 23 Input capture 0 fetched ICR06 00...

Page 708: ...FFF6EH 261 37 Reception ICR13 0000BDH FFFF68H FFFF69H FFFF6AH 448 38 Transmission FFFF64H FFFF65H FFFF66H 39 Reception ICR14 0000BEH FFFF60H FFFF61H FFFF62H 399 40 Transmission FFFF5CH FFFF5DH FFFF5EH 41 Flash memory ICR15 0000BFH FFFF58H FFFF59H FFFF5AH 576 42 Delayed interrupt generation module FFFF54H FFFF55H FFFF56H 322 Table D 1 Interrupt Vector Index 2 2 Interrupt Number Interrupt Factor Int...

Page 709: ...1E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 16LX 16 bit Microcontroller MB90895 series Hardware Manual October 2003 the first edition Published FUJITSU LIMITED Electronic Devices Edited Business Promotion Dept ...

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