Freescale Semiconductor MSC8144E, Reference Manual

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Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 11-33
11.8.8 L2 ICache Debug Access Register (L2IC_DBG_ACS)
This register is accessible only in L2 ICache debug mode.
Table 11-14 defines the L2IC_DBG_ACS
bit fields.
L2IC_DBG_ACS L2 ICache Debug Access Register Offset 0x1C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— INIT RW — DABE — DW
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— DBGAD
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 11-14. L2IC_DBG_ACS Bit Descriptions
Name Reset Description Settings
—
31–25
0 Reserved. Write to zero for future compatibility.
INIT
24
0 Debug Access Initiation
Initiates a read or write access to the cache array in
debug mode. The data should be valid before
setting this bit. The bit is ignored except in debug
mode. The bit clears on hardware cycle after it is set
by software. 0 No access.
1 Initiate access.
RW
23
0 Read/Write
Indicates whether the access is a read or a write. 0 Read.
1 Write.
—
22
0 Reserved. Write to zero for future compatibility.
DABE
21–20 0 Debug Access Byte Enable
Defines the access size. 00 Byte.
01 2 bytes.
10 4 bytes.
11 reserved.
—
19
0 Reserved. Write to zero for future compatibility.
DW
18–16
0 Debug Way
Defines
the way number of the accessed data
000 Way 0.
001 Way 1.
010 Way 2.
011 Way 3.
100 Way 4.
101 Way 5.
110 Way 6.
111 Way 7.